Received: by 2002:ac0:a581:0:0:0:0:0 with SMTP id m1-v6csp501820imm; Wed, 4 Jul 2018 00:36:21 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfbt6kdJma7ZSh0bnbOKmmCilW/WbBXSXfA9Qc3/R/lj2Zs+flSys7CG1rL9EUBr5RihC3R X-Received: by 2002:a65:62c7:: with SMTP id m7-v6mr876524pgv.286.1530689781058; Wed, 04 Jul 2018 00:36:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530689781; cv=none; d=google.com; s=arc-20160816; b=NcEpsIZBPiWBp2mPMxCW1SXy4wPI4OcxwCqDIzjVSOPORXDdM07Mq9bdgXCSJ8P+j7 /kyw0j7XxLAgMsVgolvHVrfHBn8NeJeJPZdaFUv9RhO/EiRX4f7woLpbeD19yh8TEZEy RfklRhS7ms6rAk8YDpQsFVh8wbjDU6HI/mOZGud2n0aH5hHD7ZsBeBbTGGPiOzVvwvkE 1RWzs58XHY29cXHgVVVWaXMsiaZA7RRIsAZ13eNnNfHEl3yNVGXpGYpsdsN7q1LOxiXR vQIPYl4pJ/xHaN08fp+Wgws9nncLvN0knBG4DuPjTzOJpT++N4KMbK2rUhna5wtxdTA/ 4VOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:organization:from:references:cc:to:subject :arc-authentication-results; bh=HxIlgvjGd4YUfjq6m9IzI+WyZFIyXSnkl4tZVeSFEHs=; b=y7OoBh5cYCRfWTIFpwi/pXN1c8nfRFQwsCOZnfiSK5mMLJ3xVyZW4hxedHkz5ICpfj LB5clTs+saMokqe+oNKgo9QJVYjmsE1dzwgPeofafQguPQW8c93JNBNBMBPiShsOjsbf CcMfWKkh66ljxxRa6ZzLp3g07vxB2L3VuClKxLwArbmy0y1h9u8qRq8dv2KT+Ejrl86z HOKtIHAsY8rI2Au99z/ta6QcAC3gv7nfQbjntsy9QQBgz2sPY3Vit+Li/zXI4PTsC5Kq 3rw1jV3BdiWkJrg76K0o+twAvvjAeJDrykATgkE13FkfPHke+hWPPGj6sOdxZ8sxKlmW uJPQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p17-v6si3263248pfd.76.2018.07.04.00.36.06; Wed, 04 Jul 2018 00:36:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933556AbeGDHfU (ORCPT + 99 others); Wed, 4 Jul 2018 03:35:20 -0400 Received: from foss.arm.com ([217.140.101.70]:60542 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932207AbeGDHfS (ORCPT ); Wed, 4 Jul 2018 03:35:18 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 86D157A9; Wed, 4 Jul 2018 00:35:17 -0700 (PDT) Received: from [10.1.206.75] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8EF463F5BA; Wed, 4 Jul 2018 00:35:15 -0700 (PDT) Subject: Re: [PATCH v3 4/4] arm64: dts: mediatek: add mt6765 support To: Mars Cheng , Matthias Brugger , Rob Herring , Greg Kroah-Hartman Cc: CC Hwang , Loda Chou , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, wsd_upstream@mediatek.com, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <1530669174-17623-1-git-send-email-mars.cheng@mediatek.com> <1530669174-17623-5-git-send-email-mars.cheng@mediatek.com> From: Marc Zyngier Organization: ARM Ltd Message-ID: Date: Wed, 4 Jul 2018 08:35:14 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 In-Reply-To: <1530669174-17623-5-git-send-email-mars.cheng@mediatek.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/07/18 02:52, Mars Cheng wrote: > This adds basic chip support for MT6765 SoC. > > Signed-off-by: Mars Cheng > --- > arch/arm64/boot/dts/mediatek/Makefile | 1 + > arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 ++++++ > arch/arm64/boot/dts/mediatek/mt6765.dtsi | 155 +++++++++++++++++++++++++++ > 3 files changed, 189 insertions(+) > create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts > create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi > [...] > + > + gic: interrupt-controller@c000000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + #redistributor-regions = <1>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + reg = <0 0x0c000000 0 0x40000>, // distributor > + <0 0x0c100000 0 0x200000>, // redistributor > + <0 0x0c400000 0 0x40000>; // gicc For the second time: please add *all* the GIC CPU interface regions, described in the Cortex-A53 TRM[1] (GICC, GICH, and GICV). Thanks, M. [1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0500g/ch09s02s01.html -- Jazz is not dead. It just smells funny...