Date: Fri, 12 Sep 2003 21:07:05 +0200
From: Andi Kleen <ak@suse.de>
To: Adrian Bunk <bunk@fs.tum.de>
Cc: jgarzik@pobox.com, ebiederm@xmission.com, akpm@osdl.org,
       richard.brunner@amd.com, linux-kernel@vger.kernel.org,
       torvalds@osdl.org
Subject: Re: [PATCH] 2.6 workaround for Athlon/Opteron prefetch errata
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On Fri, 12 Sep 2003 20:48:01 +0200
Adrian Bunk <bunk@fs.tum.de> wrote:


> > That's obsolete and could be removed. All 3dnow! code is dynamically patched depending on the CPUID.
> 
> Quoting e.g. arch/i386/lib/memcpy.c:
> 
> <--  snip  -->
> 
> void * memcpy(void * to, const void * from, size_t n)
> {
> #ifdef CONFIG_X86_USE_3DNOW
>         return __memcpy3d(to, from, n);
> #else
>         return __memcpy(to, from, n);
> #endif


No, it really works. The "3d" copy code uses actually MMX, which both the P4 and the K7 support fine

The only 3dnow! thing in there is that it uses 3dnow style prefetches (original MMX didn't 
have prefetches), but these are handled in a transparent way since a long time. The code just 
has an exception handler and patches them away if the prefetch ever faulted with an illegal 
instruction:


arch/i386/lib/mmx.c:

...
        __asm__ __volatile__ (
                "1: prefetch (%0)\n"            /* This set is 28 bytes */
                "   prefetch 64(%0)\n"
                "   prefetch 128(%0)\n"
                "   prefetch 192(%0)\n"
                "   prefetch 256(%0)\n"
                "2:  \n"
                ".section .fixup, \"ax\"\n"
                "3: movw $0x1AEB, 1b\n" /* jmp on 26 bytes */
                "   jmp 2b\n"
                ".previous\n"

I admit the remaining #ifdefs and comments are a bit misleading though.


-Andi
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