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[209.132.180.67]) by mx.google.com with ESMTP id be9-v6si3854672plb.67.2018.07.04.08.57.11; Wed, 04 Jul 2018 08:57:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752815AbeGDP40 (ORCPT + 99 others); Wed, 4 Jul 2018 11:56:26 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:39870 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752567AbeGDP4Z (ORCPT ); Wed, 4 Jul 2018 11:56:25 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 08A407A9; Wed, 4 Jul 2018 08:56:25 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EEFDF3F5AD; Wed, 4 Jul 2018 08:56:23 -0700 (PDT) Date: Wed, 4 Jul 2018 16:56:19 +0100 From: Mark Rutland To: Will Deacon Cc: linux-kernel@vger.kernel.org, peterz@infradead.org, boqun.feng@gmail.com, Andrea Parri Subject: Re: [PATCHv2 06/11] atomics/treewide: rework ordering barriers Message-ID: <20180704155618.higk5x3ngilbpxjo@lakrids.cambridge.arm.com> References: <20180625105952.3756-1-mark.rutland@arm.com> <20180625105952.3756-7-mark.rutland@arm.com> <20180704150645.GJ4828@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180704150645.GJ4828@arm.com> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jul 04, 2018 at 04:06:46PM +0100, Will Deacon wrote: > On Mon, Jun 25, 2018 at 11:59:47AM +0100, Mark Rutland wrote: > > Currently architectures can override __atomic_op_*() to define the barriers > > used before/after a relaxed atomic when used to build acquire/release/fence > > variants. > > > > This has the unfortunate property of requiring the architecture to define the > > full wrapper for the atomics, rather than just the barriers they care about, > > and gets in the way of generating atomics which can be easily read. > > > > Instead, this patch has architectures define an optional set of barriers, > > __atomic_mb_{before,after}_{acquire,release,fence}(), which > > uses to build the wrappers. > > Looks like you've renamed these in the patch but not updated the commit > message. Yup; Peter also pointed that out. In my branch this now looks like: ---- Instead, this patch has architectures define an optional set of barriers: * __atomic_acquire_fence() * __atomic_release_fence() * __atomic_pre_fence() * __atomic_post_fence() ... which uses to build the wrappers. ---- ... which is hopefully more legible, too! > Also, to add to the bikeshedding, would it worth adding "rmw" in there > somewhere, e.g. __atomic_post_rmw_fence, since I assume these only > apply to value-returning stuff? I don't have any opinion there, but I'm also not sure I've parsed your rationale correctly. I guess a !RMW full-fence op doesn't make sense? Or that's something we want to avoid in the API? AFAICT, we only use __atomic_{pre,post}_fence() for RMW ops today. Thanks, Mark.