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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 5 Jul 2018 12:53:47 -0400 Received: from b01ledav003.gho.pok.ibm.com (b01ledav003.gho.pok.ibm.com [9.57.199.108]) by b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w65Grkwe64421950 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 Jul 2018 16:53:46 GMT Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 536A6B2066; Thu, 5 Jul 2018 12:53:27 -0400 (EDT) Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3245DB2065; Thu, 5 Jul 2018 12:53:27 -0400 (EDT) Received: from paulmck-ThinkPad-W541 (unknown [9.85.138.104]) by b01ledav003.gho.pok.ibm.com (Postfix) with ESMTP; Thu, 5 Jul 2018 12:53:27 -0400 (EDT) Received: by paulmck-ThinkPad-W541 (Postfix, from userid 1000) id 5ACB816CA477; Thu, 5 Jul 2018 09:56:02 -0700 (PDT) Date: Thu, 5 Jul 2018 09:56:02 -0700 From: "Paul E. McKenney" To: Will Deacon Cc: Daniel Lustig , Alan Stern , Andrea Parri , LKMM Maintainers -- Akira Yokosawa , Boqun Feng , David Howells , Jade Alglave , Luc Maranget , Nicholas Piggin , Peter Zijlstra , Kernel development list Subject: Re: [PATCH 2/2] tools/memory-model: Add write ordering by release-acquire and by locks Reply-To: paulmck@linux.vnet.ibm.com References: <20180704121103.GB26941@arm.com> <20180705153140.GO3593@linux.vnet.ibm.com> <20180705162225.GH14470@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180705162225.GH14470@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-GCONF: 00 x-cbid: 18070516-0072-0000-0000-0000037A86C4 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00009314; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000266; SDB=6.01056983; UDB=6.00542257; IPR=6.00834904; MB=3.00022012; MTD=3.00000008; XFM=3.00000015; UTC=2018-07-05 16:53:50 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18070516-0073-0000-0000-0000489A6445 Message-Id: <20180705165602.GQ3593@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-07-05_06:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=812 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1806210000 definitions=main-1807050190 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jul 05, 2018 at 05:22:26PM +0100, Will Deacon wrote: > On Thu, Jul 05, 2018 at 08:44:39AM -0700, Daniel Lustig wrote: > > On 7/5/2018 8:31 AM, Paul E. McKenney wrote: > > > On Thu, Jul 05, 2018 at 10:21:36AM -0400, Alan Stern wrote: > > >> At any rate, it looks like instead of strengthening the relation, I > > >> should write a patch that removes it entirely. I also will add new, > > >> stronger relations for use with locking, essentially making spin_lock > > >> and spin_unlock be RCsc. > > > > > > Only in the presence of smp_mb__after_unlock_lock() or > > > smp_mb__after_spinlock(), correct? Or am I confused about RCsc? > > > > > > Thanx, Paul > > > > > > > In terms of naming...is what you're asking for really RCsc? To me, > > that would imply that even stores in the first critical section would > > need to be ordered before loads in the second critical section. > > Meaning that even x86 would need an mfence in either lock() or unlock()? > > I think a LOCK operation always implies an atomic RmW, which will give > full ordering guarantees on x86. I know there have been interesting issues > involving I/O accesses in the past, but I think that's still out of scope > for the memory model. > > Peter will know. Agreed, x86 locked operations imply full fences, so x86 will order the accesses in consecutive critical sections with respect to an observer not holding the lock, even stores in earlier critical sections against loads in later critical sections. We have been discussing tightening LKMM to make an unlock-lock pair order everything except earlier stores vs. later loads. (Of course, if everyone holds the lock, they will see full ordering against both earlier and later critical sections.) Or are you pushing for something stronger? Thanx, Paul