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[209.132.180.67]) by mx.google.com with ESMTP id p26-v6si5863694pgv.344.2018.07.05.11.25.44; Thu, 05 Jul 2018 11:26:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@crapouillou.net header.s=mail header.b=OdWsqM4U; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753967AbeGESYG (ORCPT + 99 others); Thu, 5 Jul 2018 14:24:06 -0400 Received: from outils.crapouillou.net ([89.234.176.41]:49708 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753769AbeGESYE (ORCPT ); Thu, 5 Jul 2018 14:24:04 -0400 Date: Thu, 05 Jul 2018 20:23:41 +0200 From: Paul Cercueil Subject: Re: [PATCH 02/14] dmaengine: dma-jz4780: Separate chan/ctrl registers To: Paul Burton Cc: Vinod Koul , Rob Herring , Mark Rutland , Ralf Baechle , James Hogan , Zubair Lutfullah Kakakhel , Mathieu Malaterre , Daniel Silsby , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Message-Id: <1530815021.6642.0@smtp.crapouillou.net> In-Reply-To: <20180703165302.3gdukxwwro5cwqba@pburton-laptop> References: <20180703123214.23090-1-paul@crapouillou.net> <20180703123214.23090-3-paul@crapouillou.net> <20180703165302.3gdukxwwro5cwqba@pburton-laptop> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1530815041; bh=GkJ0v/PlN6KmOdXHOdu7cXcDaWHEpMnzgLnjo6vl3lI=; h=Date:From:Subject:To:Cc:Message-Id:In-Reply-To:References:MIME-Version:Content-Type; b=OdWsqM4UQ/YOVatGIHcfpJ3OL21gi0eytzFYs2F+8EwCDjjwslS43wNo2ItxDEZBoUENn+96tXJp1ZyUORkrTQFHwA1jHbQaFiSgTnLioYqPUsQpCc7AwA5NdB+3jvKQQOq5moBUeglvFCEee25Dia8Wz7teqw+GmdTkOp36g+8= Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Paul, > Hi Paul, > > On Tue, Jul 03, 2018 at 02:32:02PM +0200, Paul Cercueil wrote: >> @@ -804,9 +818,19 @@ static int jz4780_dma_probe(struct >> platform_device *pdev) >> return -EINVAL; >> } >> >> - jzdma->base = devm_ioremap_resource(dev, res); >> - if (IS_ERR(jzdma->base)) >> - return PTR_ERR(jzdma->base); >> + jzdma->chn_base = devm_ioremap_resource(dev, res); >> + if (IS_ERR(jzdma->chn_base)) >> + return PTR_ERR(jzdma->chn_base); >> + >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); >> + if (!res) { >> + dev_err(dev, "failed to get I/O memory\n"); >> + return -EINVAL; >> + } >> + >> + jzdma->ctrl_base = devm_ioremap_resource(dev, res); >> + if (IS_ERR(jzdma->ctrl_base)) >> + return PTR_ERR(jzdma->ctrl_base); > > Could we have this failure case fall back to the existing behaviour > where we only have a single resource covering all the registers? That > would avoid breaking bisection between this patch & the one that > updates > the JZ4780 DT. > > For example: > > #define JZ4780_DMA_CTRL_OFFSET 0x1000 > > res = platform_get_resource(pdev, IORESOURCE_MEM, 1); > if (res) { > jzdma->ctrl_base = devm_ioremap_resource(dev, res); > if (IS_ERR(jzdma->ctrl_base)) > return PTR_ERR(jzdma->ctrl_base); > } else { > jzdma->ctrl_base = jzdma->chn_base + JZ4780_DMA_CTRL_OFFSET; > } > > Then you could remove the fallback after patch 13, to end up with the > same code you have now but without breaking bisection. > > Most correct might be to move patch 13 to right after this one, so > that > the JZ4780-specific fallback can be removed before adding support for > any of the other SoCs. Sure, I can do that for the V2. Thanks, -Paul