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Date:   Sat, 7 Jul 2018 19:51:09 +0800
From:   Guo Ren <ren_guo@c-sky.com>
To:     Peter Zijlstra <peterz@infradead.org>
Cc:     linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org,
        tglx@linutronix.de, daniel.lezcano@linaro.org,
        jason@lakedaemon.net, arnd@arndb.de, c-sky_gcc_upstream@c-sky.com,
        gnu-csky@mentor.com, thomas.petazzoni@bootlin.com,
        wbx@uclibc-ng.org, green.hu@gmail.com,
        Will Deacon <will.deacon@arm.com>
Subject: Re: [PATCH V2 06/19] csky: Cache and TLB routines
Message-ID: <20180707115108.GA3861@guoren-Inspiron-7460>
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On Thu, Jul 05, 2018 at 07:40:25PM +0200, Peter Zijlstra wrote:
> > +#ifdef CONFIG_SMP
> > +#define mb()	asm volatile ("sync.is":::"memory")
> > +#else
> > +#define mb()	asm volatile ("sync":::"memory")
> > +#endif
> 
> This is very suspect, please elaborate.
> 
> What I would've expected is:
> 
> #define mb() asm volatile ("sync" ::: "memory")
> 
> #ifdef CONFIG_SMP
> #define __smp_mb() asm volatile ("sync.is" ::: "memory")
> #endif
> 
> Is that in fact what you meant?
> 
> Do you have a reference to your architecture manual and memory model
> description somewhere?
I'll fixup it in next version patch.