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Subject: Re: [PATCH v3 3/3] clk: qcom: Add display clock controller driver for
 SDM845
To:     Stephen Boyd <sboyd@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>
Cc:     Andy Gross <andy.gross@linaro.org>,
        David Brown <david.brown@linaro.org>,
        Rajendra Nayak <rnayak@codeaurora.org>,
        Amit Nischal <anischal@codeaurora.org>,
        linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
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From:   Taniya Das <tdas@codeaurora.org>
Message-ID: <288770be-a763-b287-f62a-72ab7616efdb@codeaurora.org>
Date:   Mon, 9 Jul 2018 15:04:07 +0530
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On 7/9/2018 1:07 PM, Stephen Boyd wrote:
> Quoting Taniya Das (2018-07-09 00:07:21)
>>
>>
>> On 7/9/2018 11:46 AM, Stephen Boyd wrote:
>>>>
>>>>    > Why is the nocache flag needed? Applies to all clks in this file.
>>>>    >
>>>>
>>>> This flag is required for all RCGs whose PLLs are controlled outside the
>>>> clock controller. The display code would require the recalculated rate
>>>> always.
>>>
>>> Right. Why is the PLL controlled outside of the clock controller? The
>>> rate should propagate upward to the PLL from here, so who's going
>>> outside of that?
>>>
>> The DSI0/1 PLL are not part of the display clock controller, but in the
>> display subsystem which are managed by the DRM drivers. When DRM drivers
>> query for the rate clock driver should always return the non cached rates.
> 
> Why? Is the DSI PLL changing rate all the time, randomly, without going
> through the clk APIs to do so?
>

Hmm, I am afraid I do not have an answer for this, but this was the 
requirement to always return the non cached rates from the clock driver.

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