Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp470268imm; Mon, 9 Jul 2018 05:19:39 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcRBidfVHdYC0Yvflm2rqW9fZ6xY2LeUkOmKzPCUnZv/GO3ag1RkUdgvg03lK+UAvGMEMoB X-Received: by 2002:a17:902:d692:: with SMTP id v18-v6mr20607366ply.59.1531138779210; Mon, 09 Jul 2018 05:19:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531138779; cv=none; d=google.com; s=arc-20160816; b=c+UdP+mX/ld9SxjW+xsou/0mQX7E7ZArDY9nCeb7POOrMidO2xpRMCeW5z4AoZg0es p6FOTdYtBUUkvncFswP5leGy1PD1D2cOhjVrTvYdXtiptMoUj26QUtckI4vNmSP2w2AQ XzYN9A0d/MAFyYGqPvGT9+5LGw6XpilAsVBRsL/G7a5zaThi80OmrEhurMTfagXQZ4P+ 1ObJkKlYF/nQZHLZtMBMS2p5HuS/rQB/8OumcFrlGiwvoUaWVgJvsEPs6YBh7jHZHo6N F6G2lInCKr+T3lHSVINldg2L6qdEanEvIkjRbwjRxuwIKZ6jm4Xek0eks/YcPRAG5hlN 6r2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=tsia8fFs1tvtNDEtzDHq9lrNoZZC6PlFgn3sr+Bob7k=; b=nX3TfJaVit9+oy3ty0JBF/XGe1LB3Lra+kNOoPBaLHQpGw6xGZQAQ+k+4KhAvU4baO r2bbJAPsxnI4ZNfNZdL4Y1x8C68M5exfkxqNYpd/nQOOAozOFB/WSWV/ujPp0IQ48Vbw TxCvFjhpXHLlOkAU2bLj3BYtMPiNFJoGVifBV9QF6/kf4dnIcLx90mmDZk1c6xCrH9gm DZ7fJP5HalF9bjbELxUMVOZ8qNnda86gInNdhvYh2k42osjelcXz7nUVVefFHqewEPIc C76j2hKmZAlYUhpGERo97lGTNk5EDCQFyns7lmrVYc4Lncc1svE7CnJc5TXNko82drQF heKQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1-v6si14566950plz.379.2018.07.09.05.19.24; Mon, 09 Jul 2018 05:19:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932827AbeGIMSP (ORCPT + 99 others); Mon, 9 Jul 2018 08:18:15 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:16039 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932445AbeGIMSN (ORCPT ); Mon, 9 Jul 2018 08:18:13 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Mon, 09 Jul 2018 05:18:10 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 09 Jul 2018 05:18:12 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 09 Jul 2018 05:18:12 -0700 Received: from dhcp-10-21-25-168.Nvidia.com (10.21.25.201) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 9 Jul 2018 12:18:09 +0000 From: Aapo Vienamo To: Peter De Schrijver CC: Prashant Gaikwad , Michael Turquette , Stephen Boyd , Thierry Reding , Jonathan Hunter , , , , Aapo Vienamo Subject: [PATCH v3 1/4] clk: tegra: Fix includes required by fence_udelay() Date: Mon, 9 Jul 2018 15:17:37 +0300 Message-ID: <1531138660-9071-1-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.21.25.201] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To HQMAIL101.nvidia.com (172.20.187.10) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the missing linux/delay.h include statement for udelay() used by fence_udelay() macro. Signed-off-by: Aapo Vienamo --- drivers/clk/tegra/clk.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index e1f8846..e3b9c22 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -19,6 +19,7 @@ #include #include +#include /** * struct tegra_clk_sync_source - external clock source from codec -- 2.7.4