Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp1406125imm; Tue, 10 Jul 2018 00:58:03 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcFwvOHVXJGXI8oovNdT+CgpKx+mvRHB9+h4p5pjHMMVdiKUnUTvRyU7F+5tONR9J2TDU4h X-Received: by 2002:a62:9042:: with SMTP id a63-v6mr24714304pfe.52.1531209482943; Tue, 10 Jul 2018 00:58:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531209482; cv=none; d=google.com; s=arc-20160816; b=F7+4IFcHtGGbOj5u4SUBnte8C4CX8Qidvvmd5GXE8PxRRmF56EHb1f5VwJcMRah4uQ +dbwKT9eprsj4ZHjt1qUKqmrvW8L8aCw61LaozWxMLV463bFzF3LzLTFhhbdGysP/5NZ q28ukXAMFyJlpypGpiLFOmyS+9cntx8zeun9fuHtUmDi4IwZ0yIZukA6+hoRmfh7f9XV IrfDUBEAzfgcsVZElLA92sYJe6kwrf4XWL2wVa82zfuJEboplH1llsXrojjzAa2F1upY BlsomYX858ZweU4J2pfp6E039mms6EXdp/Rp+3LjpAdQFkyKxxQ2HNt7gkvFsGDAsr8c gdDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=OWRfHD6QVue9hE+ohf+cJrOzOec4uay/QawAdmnCPJc=; b=EMN7jGTc7rkDOScQh7X2/Z72MqY1/843cg/Mt53/LyyUW9JmQNtbdA8g5Io2fhjOns Do/S1cuoskqTZHw8Pe/yBWleAaAlNWk/oeeHV0e6s3A5YzP09EvIAfRhJJg79FeY/woy v4rzimMHjPrtLpDzF1+bMl7J3VPbOu9qkYcwWozQawIcoedkKaxnnZYqEmHdRVfHp707 szS+brtpKLPMv1bq0HU7MjsrvX1XNo+yI3qV8U2BUWiutlQtNvBmU5yh343uoickeXJY IRoji+FIP3hPASL1yk3QHaDn1MWacyHOES5pf0UEj+TWJjx5wDo44ySUBrjFuAomlIhq A4kQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m141-v6si17747944pfd.310.2018.07.10.00.57.47; Tue, 10 Jul 2018 00:58:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751214AbeGJHz6 (ORCPT + 99 others); Tue, 10 Jul 2018 03:55:58 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:59118 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751057AbeGJHz5 (ORCPT ); Tue, 10 Jul 2018 03:55:57 -0400 X-UUID: 46e210b57caa4ccba2c25fcb05ebfe55-20180710 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1932035705; Tue, 10 Jul 2018 15:55:52 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 10 Jul 2018 15:55:50 +0800 Received: from mtkslt306.mediatek.inc (10.21.14.136) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 10 Jul 2018 15:55:50 +0800 From: Ryder Lee To: Matthias Brugger CC: Rob Herring , Sean Wang , , , , , Ryder Lee Subject: [PATCH 2/2] arm64: dts: mt7622: update a clock property for UART0 Date: Tue, 10 Jul 2018 15:55:48 +0800 Message-ID: X-Mailer: git-send-email 1.9.1 In-Reply-To: <2ff39c40ef6bc3054667e63c785a1d28527b5ddf.1531209126.git.ryder.lee@mediatek.com> References: <2ff39c40ef6bc3054667e63c785a1d28527b5ddf.1531209126.git.ryder.lee@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The input clock of UART0 should be CLK_PERI_UART0_PD. Signed-off-by: Ryder Lee --- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 8cdec52..4caa9b4 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -367,7 +367,7 @@ reg = <0 0x11002000 0 0x400>; interrupts = ; clocks = <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART1_PD>; + <&pericfg CLK_PERI_UART0_PD>; clock-names = "baud", "bus"; status = "disabled"; }; -- 1.9.1