Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp1442010imm; Tue, 10 Jul 2018 01:43:24 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdMV13gQJVUxFF0n79Vq+dxvFcPJ7h5PTMGa3i2pFAXrMLhIfK3MG0kQk3ab1SwbdNXdxxC X-Received: by 2002:a17:902:8ecb:: with SMTP id x11-v6mr24356151plo.308.1531212204780; Tue, 10 Jul 2018 01:43:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531212204; cv=none; d=google.com; s=arc-20160816; b=Cs/KEeRb7aQd3Ssla6TxpIlrjpdHBpP5VsTbPGizIZJvT7Ipja23psrmO9MnujCaUf yL/ZZx9J8zyyE0y5TDRNZ40I0CRkIkJ+fEZmQc8AvaJ5Yyom71syUMXSgsyeOovBcn8H rVYAy6V7nNZo6Wwj9HRInPytfq/VJj4JR8ZyAqGZY/mZDMi3eJfmqIaOxVY8atOddVBR PSnN2lHab8G/faWzsnMcTB2BaHXy3gf01nx8VjN3rrlAO1xGaXMHY5QNE5vHpBFHX3Ri 5twks5u/z2txRKiSCvVV4l7FRXTCCIefhtb95vfOOFb1uQojCi+H/hCdVWlmxnk3Cj0Y JXDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=s0UE9oMgpgB39M23iRYFmrijMQRPFbKkRvMKOSNmoJ4=; b=glf7da7ahOLDOrPDGwin/Q7zotBKpNdKeU4plvkUEqhUvynpZMRvJ9OFfeyZBuzZfR +oNN1kGbZaeYo/Dv9g41h7nDoJCNDaqqDA78CPIbi3bCvrI8KpdSmKucN5TkQlYhAOEN TuT9N/ZKBppvk1PfObIg9cp6SwwZGNmWVggtdATmMUKWfzxiYPWylViPl4C0lzfr518R V0mWBhQeY7vw+oxDKk11+rZedtTW0PpDlJAZHseTGlsoiTzFNHbKjhF+hRlxHpbPhf88 tvo80oAPkTNCSPdPVsUMViuY4Vx306XZGb+ePELES7JhSctm/QtQs0/BUxYuEJY6LBOh fQsg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a15-v6si2835579pgg.611.2018.07.10.01.43.09; Tue, 10 Jul 2018 01:43:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933095AbeGJIkn (ORCPT + 99 others); Tue, 10 Jul 2018 04:40:43 -0400 Received: from mail-sh2.amlogic.com ([58.32.228.45]:19720 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751242AbeGJIkO (ORCPT ); Tue, 10 Jul 2018 04:40:14 -0400 Received: from localhost.localdomain (10.18.20.250) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server id 15.0.1320.4; Tue, 10 Jul 2018 16:39:25 +0800 From: Yixun Lan To: Jerome Brunet , Neil Armstrong CC: Yixun Lan , Kevin Hilman , Carlo Caione , Michael Turquette , Stephen Boyd , Rob Herring , Miquel Raynal , Boris Brezillon , Martin Blumenstingl , Liang Yang , Qiufang Dai , Jian Hu , , , , , Subject: [PATCH v2 2/3] clk: meson: add sub MMC clock dt-bindings IDs Date: Tue, 10 Jul 2018 16:36:57 +0000 Message-ID: <20180710163658.6175-3-yixun.lan@amlogic.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180710163658.6175-1-yixun.lan@amlogic.com> References: <20180710163658.6175-1-yixun.lan@amlogic.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.18.20.250] Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add two clock bindings IDs which provided by the MMC clock controller, These two clocks will be used by MMC or NAND driver. Signed-off-by: Yixun Lan --- .../dt-bindings/clock/amlogic,meson-mmc-clkc.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 include/dt-bindings/clock/amlogic,meson-mmc-clkc.h diff --git a/include/dt-bindings/clock/amlogic,meson-mmc-clkc.h b/include/dt-bindings/clock/amlogic,meson-mmc-clkc.h new file mode 100644 index 000000000000..2ae988ebc3ae --- /dev/null +++ b/include/dt-bindings/clock/amlogic,meson-mmc-clkc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Meson MMC sub clock tree IDs + * + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + * Author: Yixun Lan + */ + +#ifndef __MMC_CLKC_H +#define __MMC_CLKC_H + +#define CLKID_MMC_DIV 1 +#define CLKID_MMC_PHASE_TX 3 +#define CLKID_MMC_PHASE_RX 4 + +#endif -- 2.18.0