Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp1654383imm; Tue, 10 Jul 2018 05:50:48 -0700 (PDT) X-Google-Smtp-Source: AAOMgpezVtTwmzaJw4Eg8WISXxxxKBQh5hUWEgAJCLlkLvevyh9k8Zt3cdpeNVC5vJRPL8Wa3d1K X-Received: by 2002:a17:902:3281:: with SMTP id z1-v6mr24866790plb.226.1531227048503; Tue, 10 Jul 2018 05:50:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531227048; cv=none; d=google.com; s=arc-20160816; b=slZyYQI/P1ZlSL+hlPLcnSlz+7lDw09xnIYFOfPrrIUQ8LEJM8ovB87EYJiVftcopI NufNMji66+qby0KXjHdGTDmoau+X0Zv8ANNDS+7reQUcBQUkJjnWkOY30jH+lxRi/DLN n1h8/eWWT1EhyVTSiE41g9n8UGLTTBW7ZNJZ7wOWeIllKYW2Jri+w0xAcD/nV26Lgxnl T1f6z4AYUq8d4A1VYy3nNeLCnQEZJQl7CCGX9dlhDf7ifC+PIMyaDnL2I86CxucPVnqc WNJNp4yf9p9C1brSNZuQ7mqTEEVa1en1Yhooiq2Q6ELqsZnJ8zwu5nun5Nwo/EgPySkD 6dkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=5Qo3kFh94L7u0Z3kIt1PWkStf1LasULw+hGSudeSc9s=; b=yZGgLqDGcDL+xdeG90b6W/aO2AFT6B4tJ3fKQJlp2YJ2wvGioRYKkcuL4vYDRFJEpI PD/QW177sT4mAeup0xvRQnh9wTksc/4IOgFCrtnygpEz1T/ZkWadIiolx+AXvqIEMhDU PlNqF9bGh/Zz4/Fx5QcEbFQHXQiLTiMcjjZbdXZsv95pwTFGr2009FRpsfCvUEf+Bfr0 cx9u8fjWCqiaWj/W1ZOydCDCTZfBvhr9OA2Iya7mBTH0dybzz6I3PvhfAF9co4lwQof6 +8coFVMEPDVGgZXbUmqmAKlmtyktLR9lACaJPU9OkEHWQy9xL3nXXIao5PoE6yWQLHvc Hu1g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g87-v6si8660923pfg.225.2018.07.10.05.50.33; Tue, 10 Jul 2018 05:50:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933268AbeGJMsh (ORCPT + 99 others); Tue, 10 Jul 2018 08:48:37 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:18447 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932752AbeGJMse (ORCPT ); Tue, 10 Jul 2018 08:48:34 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Tue, 10 Jul 2018 05:48:29 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 10 Jul 2018 05:48:34 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 10 Jul 2018 05:48:34 -0700 Received: from dhcp-10-21-25-168.Nvidia.com (10.21.25.201) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 10 Jul 2018 12:48:31 +0000 From: Aapo Vienamo To: Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Mikko Perttunen CC: Aapo Vienamo , , , Subject: [PATCH 0/6] Tegra PMC pinctrl pad configuration Date: Tue, 10 Jul 2018 15:47:53 +0300 Message-ID: <1531226879-11802-1-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.21.25.201] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To HQMAIL101.nvidia.com (172.20.187.10) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi all, The Tegra Power Management Controller (PMC) can set pad power states and voltage configuration. This series implements pinctrl interfaces for configuring said pad properties. Aapo Vienamo (6): soc/tegra: pmc: Fix pad voltage configuration for Tegra186 soc/tegra: pmc: Factor out DPD register bit calculation soc/tegra: pmc: Implement tegra_io_pad_is_powered() soc/tegra: pmc: Use X macro to generate IO pad tables dt-bindings: Add Tegra PMC pad configuration bindings soc/tegra: pmc: Implement pad configuration via pinctrl .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 84 ++++ .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 95 ++++ drivers/soc/tegra/pmc.c | 504 ++++++++++++++++----- include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h | 18 + include/soc/tegra/pmc.h | 1 + 5 files changed, 580 insertions(+), 122 deletions(-) create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h -- 2.7.4