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[209.132.180.67]) by mx.google.com with ESMTP id o16-v6si16471069pll.449.2018.07.10.11.23.28; Tue, 10 Jul 2018 11:23:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=XMO0dS5n; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732573AbeGJSVU (ORCPT + 99 others); Tue, 10 Jul 2018 14:21:20 -0400 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:52737 "EHLO esa6.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732245AbeGJSVU (ORCPT ); Tue, 10 Jul 2018 14:21:20 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1531246873; x=1562782873; h=subject:to:cc:references:from:message-id:date: mime-version:in-reply-to:content-transfer-encoding; bh=jmihC36F+iYYCODOceHXNgNSGIYkSW0HINSAs/sg9rE=; b=XMO0dS5n/fdCTH08Q12DWpCnnY9qJcUA8tDKcOadKkc2pIWaNyUV+rH7 hiEl4KqvmhhQMCgLlxhKiQVrbOzOqA1wxEupVCvciPszVFyznsgxNyrp9 M/bpfdWW3bKxgbiAL8uf+WuW+FRsSUF2Pry6LZKqtsItDoy4OATGkndZA jNHb/OW9r07gVIXHlBwBVGKP5qyLM71GfKaLrevBanHwbWP+wudNqR6TC kD8RYlkVJbzgl9Zq7q5wV+ebbCLCwxHF3bq0He0VfFC8yZLRBd8o+dCsW rYjXC9TAPOu/Tx9EOguD56AWRGbkOHc+sVGuQQfYmkqEltZYKMHtQ0XGn w==; X-IronPort-AV: E=Sophos;i="5.51,335,1526313600"; d="scan'208";a="84941339" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 11 Jul 2018 02:12:08 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP; 10 Jul 2018 11:00:57 -0700 Received: from c02v91rdhtd5.sdcorp.global.sandisk.com (HELO [10.196.157.210]) ([10.196.157.210]) by uls-op-cesaip02.wdc.com with ESMTP; 10 Jul 2018 11:12:08 -0700 Subject: Re: [RFC PATCH 0/4] Stop losing firmware-set DMA masks To: Christoph Hellwig , Robin Murphy Cc: "devicetree@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , "gregkh@linuxfoundation.org" , "joro@8bytes.org" , "x86@kernel.org" , "linux-kernel@vger.kernel.org" , "linux-acpi@vger.kernel.org" , "iommu@lists.linux-foundation.org" , "robh+dt@kernel.org" , Palmer Dabbelt , "hanjun.guo@linaro.org" , "sudeep.holla@arm.com" , "linux-riscv@lists.infradead.org" , "frowand.list@gmail.com" , "linux-arm-kernel@lists.infradead.org" , "m.szyprowski@samsung.com" References: <20180710180232.GA26285@lst.de> From: Atish Patra Message-ID: <1469c385-a586-3192-6ec8-cb15878acafe@wdc.com> Date: Tue, 10 Jul 2018 11:12:07 -0700 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.12; rv:52.0) Gecko/20100101 Thunderbird/52.9.0 MIME-Version: 1.0 In-Reply-To: <20180710180232.GA26285@lst.de> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 7/10/18 11:01 AM, Christoph Hellwig wrote: >> These patches attempt to deal with this in the simplest way possible by >> generalising the specific quirk for 32-bit bridges into an arbitrary >> mask which can then also be plumbed into the firmware code. In the >> interest of being minimally invasive, I've only included a point fix >> for the IOMMU issue as seen on arm64 - there may be further tweaks >> needed in DMA ops to catch all possible incarnations of this problem, >> but this initial RFC is mostly about the impact beyond the dma-mapping >> subsystem itself. > > Thanks, this looks very nice to me. > > In fact it probably solves the RISC-V/Xiling problem as well if we can > just add the dma-ranges property to the device tree for the affected > systems. Palmer, do you know how easily the DT could be updated for > that case? > Hi Chris, I have a PR in riscv-pk that can modify the DT in bbl easily. In fact, that's how I added the timer node for the interrupt patch. https://github.com/riscv/riscv-pk/pull/112 Obviously, the best approach would be to update the firmware but that may be time consuming sometime. Regards, Atish >> >> Robin. >> >> >> [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/580804.html >> [2] http://lists.infradead.org/pipermail/linux-arm-kernel/2016-December/474443.html >> >> Robin Murphy (4): >> dma-mapping: Generalise dma_32bit_limit flag >> ACPI/IORT: Set bus DMA mask as appropriate >> of/device: Set bus DMA mask as appropriate >> iommu/dma: Respect bus DMA limit for IOVAs >> >> arch/x86/kernel/pci-dma.c | 2 +- >> drivers/acpi/arm64/iort.c | 1 + >> drivers/iommu/dma-iommu.c | 3 +++ >> drivers/of/device.c | 1 + >> include/linux/device.h | 6 +++--- >> kernel/dma/direct.c | 2 +- >> 6 files changed, 10 insertions(+), 5 deletions(-) >> >> -- >> 2.17.1.dirty > ---end quoted text--- > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv >