Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp1108614imm; Wed, 11 Jul 2018 17:35:56 -0700 (PDT) X-Google-Smtp-Source: AAOMgpd18wbwPqg1i4btHqdDvx+/1HOixUeqFWXQv2QbU7C5msPDBR2B6BMZBrNumFA8CEa/cudd X-Received: by 2002:a17:902:3381:: with SMTP id b1-v6mr78121plc.248.1531355756813; Wed, 11 Jul 2018 17:35:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531355756; cv=none; d=google.com; s=arc-20160816; b=h6MmzxkbQWylAKsM752YDHpPuewbzrzkvm/JNSAa/vNwIGl44Ej9m4RMkmVPBNo78+ Z5L3kz5c6bQ3Fp/c73i8DLejZNRbRmWK/Pr9oZoSdjBD1QNdUh75RoQ2tkshAc4t7Mk1 TWUX8RZNK8Pp3WekTEOLA35iCBvV5xm54DlYPsDkeP0/bWWnRY8mm6g3vQNJs1RLDwAJ 0SP5rCjqRMuqG9GW/Ueq66LFASzz+bl/2f/runScwrK9GthI1IjfJRx+WeZtQeq7AM2z Bt7NYJRwle3vIt/z/HYO5u3g6xrtu3u+rHaeSukrS9kJYFi0SEBmXPTDKS2E9RIHG6nN GMqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:in-reply-to :subject:cc:to:from:date:arc-authentication-results; bh=ft8u5ACY/JvHN1xLNHV8KPmi2sgVBd8WqiDVrhYoTbQ=; b=DUMsKxli2HZrTGGqKzWZwKr/pFwRBziStiu/GzLx3YWiYYebj1mDtMnVWyJMlewbIu ahp7TlCQwAfM6w0xDj7FAWyAizIxXh1w1E0xZCHtYtDNQ2Zxx4b7hjfdvcJxgc0nQJ23 vV3V43eSgtNauq5QHyjlwh/bTNMPox/5yysOCGPw4jHqdbPzco9XwYM/FhYvDe2cNDAZ Kyjtifqvx8g4nq/+8Da1kZbbf5YF4ppkmtnLKetTQoEOYtfjtMfkBvspH/oCqHIrZDf6 HIM9oESwI1NNJsEEe6cR+sO9ialuDDgr/p36KtQ8cJGxHB+FU/F33+YdnjGP53oVZD9a pDXA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q28-v6si12895848pgm.362.2018.07.11.17.35.41; Wed, 11 Jul 2018 17:35:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733178AbeGKRlh (ORCPT + 99 others); Wed, 11 Jul 2018 13:41:37 -0400 Received: from iolanthe.rowland.org ([192.131.102.54]:43854 "HELO iolanthe.rowland.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1732860AbeGKRlh (ORCPT ); Wed, 11 Jul 2018 13:41:37 -0400 Received: (qmail 6754 invoked by uid 2102); 11 Jul 2018 13:36:14 -0400 Received: from localhost (sendmail-bs@127.0.0.1) by localhost with SMTP; 11 Jul 2018 13:36:14 -0400 Date: Wed, 11 Jul 2018 13:36:14 -0400 (EDT) From: Alan Stern X-X-Sender: stern@iolanthe.rowland.org To: David Laight cc: "Paul E. McKenney" , LKMM Maintainers -- Akira Yokosawa , Andrea Parri , Boqun Feng , Daniel Lustig , David Howells , Jade Alglave , Luc Maranget , Nicholas Piggin , Peter Zijlstra , Will Deacon , Kernel development list Subject: RE: [PATCH v3] tools/memory-model: Add extra ordering for locks and remove it for ordinary release/acquire In-Reply-To: <3344e7aeb09644758860ac343bd757a1@AcuMS.aculab.com> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 11 Jul 2018, David Laight wrote: > > From: Alan Stern > > Sent: 10 July 2018 19:18 > > More than one kernel developer has expressed the opinion that the LKMM > > should enforce ordering of writes by locking. In other words, given > > the following code: > > > > WRITE_ONCE(x, 1); > > spin_unlock(&s): > > spin_lock(&s); > > WRITE_ONCE(y, 1); > > > > the stores to x and y should be propagated in order to all other CPUs, > > even though those other CPUs might not access the lock s. In terms of > > the memory model, this means expanding the cumul-fence relation. > > The usual 'elephant in the room' is Alpha. > I don't claim to understand the alpha memory model but it wouldn't > surprise me if the above is impossible to implement on alpha. It's not impossible, since Alpha does have a full memory barrier instruction (and the implementation uses it). Alan