Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp1605583imm; Thu, 12 Jul 2018 05:01:08 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcCOj1o66jDwBK04j1MFX8PfIcYqD+kZti/OrzO7UXrql+/MmA/E/BQUU9bQkiGxceEPsAu X-Received: by 2002:a17:902:1101:: with SMTP id d1-v6mr1873000pla.147.1531396867980; Thu, 12 Jul 2018 05:01:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531396867; cv=none; d=google.com; s=arc-20160816; b=T2kgzL/Pv1MwxNpIGBuqhcNwJ0EM4FoaQp6MSEQ1gWnrL3mY8Xyqx56snT/J0IHiyk 27EiN/Hgj6mXwriMOfROxRuCxThrYjZf6c3D3xVYq1aUbS/07ozE/+0AKJK2Tjhh167n AjxBES8ZqpbBEUn2HyPru8NGlxEt5X5C9+AgrNQCAa104FodmExGSOZbajbCNGhwkb0K 9wLE1hOgUr6YX5dRkM5HWu4YXqU11TyRZGr6S+Zqp0mLlfs3dPJxc2MlnKNMCAloEL2l KHrpFcRwCjPifm3hlmcwj2VoAANWAqGYAPu9i94i+pM6Jm1XTZapF1qx4l9rvejA17F+ ocRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=X2Qv6kbKdYZe05mHv5e9TIxaG6UM5ON4SVZFijpNUSA=; b=kdOOzXTW0sdhCXPXgWliRDBQa5eSfKh3F3OQkqDFY3dqKD40x2jLWHtUbomraAqmy0 GN1lnVqReXI74mcHI0biL6CxRb1cmaXFoPMxLkaqA+45NlfEwIsibIgEgIzGyXYI/wzQ Xy6wQHflt/FyEfpwZML6RPU8YwGB+qGR2zwJzs2VZvGx93L9LnA9CLiW4bOncn/ONOZq gF3BDjlxCeXP+seY+SIyoMfOkomktvAmMenf5BauO4/7/9tCgdhQT1xVpNIvP9tF0fe4 jgTqCKzTGoAMcj7FF4eH48bZyPjDmXNfwRM0wV26mAQ0RRvpurHWlWAVzKXVofak2Izk Gqpw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u123-v6si20844297pgb.414.2018.07.12.05.00.52; Thu, 12 Jul 2018 05:01:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727366AbeGLMJe (ORCPT + 99 others); Thu, 12 Jul 2018 08:09:34 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:16188 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726696AbeGLMJd (ORCPT ); Thu, 12 Jul 2018 08:09:33 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Thu, 12 Jul 2018 04:59:33 -0700 Received: from HQMAIL107.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 12 Jul 2018 05:00:18 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 12 Jul 2018 05:00:18 -0700 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 12 Jul 2018 12:00:18 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Thu, 12 Jul 2018 12:00:18 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 12 Jul 2018 05:00:18 -0700 From: Aapo Vienamo To: Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Mikko Perttunen , Laxman Dewangan CC: Aapo Vienamo , , , Subject: [PATCH v3 0/7] Tegra PMC pinctrl pad configuration Date: Thu, 12 Jul 2018 15:00:06 +0300 Message-ID: <1531396813-6581-1-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi all, The Tegra Power Management Controller (PMC) can set pad power states and voltage configuration. This series implements pinctrl interfaces for configuring said pad properties. Changelog v3: - Don't expose tegra_io_pad_is_powered() - Remove tegra_io_pad_set_voltage() stub from pmc.h - Fixes i386 build failure reported by kbuild test robot v2: - Add Tegra186 AO_HV pad - Make the IO pad tables narrower - Add parens to TEGRA_IO_PAD() and TEGRA_IO_PIN_DESC() - Fix a typo in the dt-bindings docs - Remove old pmc pad voltage configuration APIs - Check return value of tegra_io_pad_find() in tegra_io_pad_pinconf_get()/_set() Aapo Vienamo (7): soc/tegra: pmc: Fix pad voltage configuration for Tegra186 soc/tegra: pmc: Factor out DPD register bit calculation soc/tegra: pmc: Implement tegra_io_pad_is_powered() soc/tegra: pmc: Use X macro to generate IO pad tables dt-bindings: Add Tegra PMC pad configuration bindings soc/tegra: pmc: Remove public pad voltage APIs soc/tegra: pmc: Implement pad configuration via pinctrl .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 84 ++++ .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 95 ++++ drivers/soc/tegra/pmc.c | 512 +++++++++++++++------ include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h | 18 + include/soc/tegra/pmc.h | 20 +- 5 files changed, 581 insertions(+), 148 deletions(-) create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h -- 2.7.4