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[209.132.180.67]) by mx.google.com with ESMTP id f14-v6si20881029pgr.290.2018.07.12.10.15.44; Thu, 12 Jul 2018 10:15:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732538AbeGLRYh (ORCPT + 99 others); Thu, 12 Jul 2018 13:24:37 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:53826 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732417AbeGLRYh (ORCPT ); Thu, 12 Jul 2018 13:24:37 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D70F0ED1; Thu, 12 Jul 2018 10:14:09 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A77103F589; Thu, 12 Jul 2018 10:14:09 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 131661AE2F86; Thu, 12 Jul 2018 18:14:52 +0100 (BST) Date: Thu, 12 Jul 2018 18:14:52 +0100 From: Will Deacon To: Alan Stern Cc: Peter Zijlstra , Andrea Parri , "Paul E. McKenney" , LKMM Maintainers -- Akira Yokosawa , Boqun Feng , Daniel Lustig , David Howells , Jade Alglave , Luc Maranget , Nicholas Piggin , Kernel development list , Linus Torvalds Subject: Re: [PATCH v2] tools/memory-model: Add extra ordering for locks and remove it for ordinary release/acquire Message-ID: <20180712171451.GI26935@arm.com> References: <20180712134821.GT2494@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Alan, On Thu, Jul 12, 2018 at 01:04:27PM -0400, Alan Stern wrote: > On Thu, 12 Jul 2018, Peter Zijlstra wrote: > > But as you (and Will) point out, we don't so much care about rmw-acquire > > semantics as much as that we care about unlock+lock behaviour. Another > > way to look at this is to define: > > > > smp-store-release + rmw-acquire := TSO (ideally smp_mb) > > > > But then we also have to look at: > > > > rmw-release + smp-load-acquire > > rmw-release + rmw-acquire > > Let's assume that rmw-release is equivalent, in terms of ordering > strength, to smp_store_release(). Then we can focus our attention on > just the acquire part. I can live with that, but it does add another special case, where we could otherwise just special case acquire/release for the load/store variants vs everything else. > On PowerPC, for instance, if spin_lock() used a full HWSYNC fence > then unlock+lock would become RCsc -- even with no changes to > spin_unlock(). > > > for completeness sake, and I would suggest they result in (at least) the > > same (TSO) ordering as the one we really care about. > > > > One alternative is to no longer use smp_store_release() for unlock(), > > and say define atomic_set_release() to be in the rmw-release class > > instead of being a simple smp_store_release(). > > > > Another, and I like this proposal least, is to introduce a new barrier > > to make this all work. > > This apparently boils down to two questions: > > Should spin_lock/spin_unlock be RCsc? I would love that to be the case, but I'm not asking you to fight that battle :) > Should rmw-acquire be strong enough so that smp_store_release + > rmw-acquire is RCtso? > > If both answers are No, we end up with the v3 patch. If the first > answer is No and the second is Yes, we end up with the v2 patch. The > problem is that different people seem to want differing answers. Just to be extra unhelpful: I'm happy with either v2 or v3. I suspect Daniel is the one to convince on v2, because it's RISC-V that's affected by this. Will