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[209.132.180.67]) by mx.google.com with ESMTP id b17-v6si21787171pgn.308.2018.07.12.10.17.11; Thu, 12 Jul 2018 10:17:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@google.com header.s=20161025 header.b=kaqRUP81; dkim=fail header.i=@chromium.org header.s=google header.b=L3C71xn5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732471AbeGLR0P (ORCPT + 99 others); Thu, 12 Jul 2018 13:26:15 -0400 Received: from mail-vk0-f65.google.com ([209.85.213.65]:42664 "EHLO mail-vk0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727092AbeGLR0P (ORCPT ); Thu, 12 Jul 2018 13:26:15 -0400 Received: by mail-vk0-f65.google.com with SMTP id t4-v6so16653431vke.9 for ; Thu, 12 Jul 2018 10:15:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=YYiSlz0Wkyrm77lIMGDpvJWBOeQvsof50ruEHd8VCrc=; b=kaqRUP817toUkpqle5B3I7WCUovQgCtztzGU875qiZFSZzgLc4N2Cs8XQrXo/VPJ1i k20ZFEE9U2MMRVY+ACL0/lL7RndAHIM4amPfz2J2EImgksuiXhWDnq2n5ztpmYxMmHmn NMROMEbqBLSCvfGtZBEbnzaI5sBxwHFLYMUAYPeGWhFlnvQusYjPoFlP+LFZL1JzY4jn xZnVNLP9c1QsN9FdQHhXgJkfiqjodZtCZVbfAxwC4WI0B3H7ew0do//ZVxoFtWtV/6Qa IRAMwXcv5mzeT+ADpdcqSFz+V04VihjG1T56wl3MnIxTQKqj0fDrDS5A5qlFT9OCsnCX 7Jhg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=YYiSlz0Wkyrm77lIMGDpvJWBOeQvsof50ruEHd8VCrc=; b=L3C71xn5ujPAzPT+z3ULUa/kJM8W8p5IU6Kd4VpbJYW8T5WZs5qxPNKNswfKSJ2lVb tu+4On9KbRuL9GnvTfVpGxK5NLjGF0y67TFmYzE/B8NbEnR1p4xupWKIYJd0GaBS495h mw6hjZ9d/prQHP7BgXAlKDvBIFM3YityQG7t8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=YYiSlz0Wkyrm77lIMGDpvJWBOeQvsof50ruEHd8VCrc=; b=m087GJn3UY7SNgJoTBeoDxkqTKTZsXO1h2ltd6fV6YVI6fM8BaN+By0qGDcUMzhpzs ww+3Oie7RB+KKHD2NubdySOy5V+q6jwsbrERfDz5TBpUEwWtXtrw28F2jflA8aHhBQm5 BknM0MnNJxzdkN/wmEf9wZEy1/vG565KJZ3LPwt0U7Y7qJlEdI+KQZiRL1zCR71cslyb NK8WH/Q0GTmkYyuxllsk/TOMJi3p5t9gfELdV4LmvLM3WtxxRWkeuY0VIlQjvA+o95Pb m8lLhgegAQNAT9y9/16EksvLH6W2bQ2R3Ra46q7Dkg1nNPCGEqwTb6bahVeuFwTMnb6S HsxA== X-Gm-Message-State: AOUpUlGjyJcEu4gJDb1KFjPPv39yU9f5+CBBovAE4eYaj2lebQXqIYiZ W2jwlxa98pt3TMqkKUddhN/x426zaLi8IcSb9mLEQw== X-Received: by 2002:a1f:5347:: with SMTP id h68-v6mr1719655vkb.141.1531415746308; Thu, 12 Jul 2018 10:15:46 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a1f:9495:0:0:0:0:0 with HTTP; Thu, 12 Jul 2018 10:15:45 -0700 (PDT) In-Reply-To: References: From: Doug Anderson Date: Thu, 12 Jul 2018 10:15:45 -0700 X-Google-Sender-Auth: 2yZh3WlKGbgPjHJBmqiZuaB-A2E Message-ID: Subject: Re: [PATCH v7 5/7] dt: thermal: tsens: Document the fallback DT property for v2 of TSENS IP To: Amit Kucheria Cc: LKML , Rajendra Nayak , linux-arm-msm , Bjorn Andersson , Eduardo Valentin , smohanad@codeaurora.org, Vivek Gautam , Andy Gross , Matthias Kaehlcke , Zhang Rui , Rob Herring , Mark Rutland , linux-pm@vger.kernel.org, devicetree@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Thu, Jul 12, 2018 at 1:39 AM, Amit Kucheria wrote: > We want to create common code for v2 of the TSENS IP block that is used in > a large number of Qualcomm SoCs. "qcom,tsens-v2" should be able to handle > most of the common functionality start with a common get_temp() function. > > It is also necessary to split out the memory regions for the TM and SROT > register banks because their offsets are not constant across SoC families. > > Signed-off-by: Amit Kucheria > Reviewed-by: Rob Herring > Reviewed-by: Bjorn Andersson > Tested-by: Matthias Kaehlcke > --- > .../devicetree/bindings/thermal/qcom-tsens.txt | 31 +++++++++++++++++----- > 1 file changed, 25 insertions(+), 6 deletions(-) Reviewed-by: Douglas Anderson