Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp2069017imm; Thu, 12 Jul 2018 12:43:15 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeVeogt1rhU1XLBVggwrZUDbSZw3VbbPJx+bqBy+1mW39qsKu+ZdtoXf7FiqsOxByUOucrC X-Received: by 2002:a63:4a61:: with SMTP id j33-v6mr3282242pgl.436.1531424595169; Thu, 12 Jul 2018 12:43:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531424595; cv=none; d=google.com; s=arc-20160816; b=VwD18j8SaitcrUzgCTJrv1aSgTFSL/FUigyBB0JRHRjWBbee2ydJCw3M5reev0PZor QV9/pWAOimBZgBtQak1DkmXh8xOEg/xtHnVR50oD0esGqDfSh1S8/cUNFDGIHBqWKI39 UrqimGGKX8NqSz5/iYmA0JA63g3zOMuPPO4M2dMAwmbA+zqO/+yqUe6zNcFePW8D5cPh jT3h95T7ZZLJLY/pwtsc3hkCssHgQ16hUAAnjvDQNb7T1kBVnwQz4AbdYTByZgMJF3Ul R+zy2KZK9pWUT77YPqL2zcFViAIES6Jx7JETG9gmHx0qT/ESJpgAHplnIhL91+g8uu6q j9vQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:date:subject:user-agent:message-id :references:cc:in-reply-to:from:to:content-transfer-encoding :mime-version:dkim-signature:arc-authentication-results; bh=XLrkWWQ7xU86B7+DIoSqIUvjUw5fpnXGH5i/20FmZGI=; b=wKnp/PwFyJxmKfSpOGMgwWyf9HCiUrFgXgw18oYAhvJEG1tlzQsQSIPw+xwcM4vZnM ipqI5JGnEQZND0vM7tzBhJOMdycT15EsvaO6BtAzVxck/BgmB8kXI6P1YhTSXTQCETn6 n9AXf2S+nKY4ylrgQc1cm1GGKLvPg6RLlOpHq1XnjOAcIDhQ3wXEgKwMcvgQ0s0vksdT pIl+alehH5V3FPEdWiRJdEt4NtFUamx9cKhFlTKIocW0cD9ch1qKG18NT/crSafmP/Fo lr+sGPJoxINmtYkFYRN0XQmu4lDthYyz0wF0/3P85ppuZ0uoPdLRGgIQGEh1CitJ/FGQ 6uSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=Uqjp3vMA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g8-v6si23103512pfj.283.2018.07.12.12.42.58; Thu, 12 Jul 2018 12:43:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=Uqjp3vMA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732324AbeGLTwj (ORCPT + 99 others); Thu, 12 Jul 2018 15:52:39 -0400 Received: from mail.kernel.org ([198.145.29.99]:41456 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726583AbeGLTwi (ORCPT ); Thu, 12 Jul 2018 15:52:38 -0400 Received: from localhost (unknown [104.132.1.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 868062124D; Thu, 12 Jul 2018 19:41:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1531424497; bh=zw7Wf1MRYU3yWh3N3KpfhaIw9aQcelIrq10eM7LE4r8=; h=To:From:In-Reply-To:Cc:References:Subject:Date:From; b=Uqjp3vMAwEJebGlgG8OM+DHX9i7p8yA9No/MwzktgAILMLxHYsEUhfRRZfll5XOy6 45CdTSi0JThh3B/QjMGYNaw/1m7U9JDxAvjltlU2coXPO+BU5jZThkUNIUtTUKcW98 m+ayNLiQjHE/KnbwqQ4YdkBQIUX9Ps8vjkIII26Q= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: Abhinav Kumar , Michael Turquette , Sandeep Panda , Taniya Das , ryadav@codeaurora.org From: Stephen Boyd In-Reply-To: Cc: Andy Gross , David Brown , Rajendra Nayak , Amit Nischal , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <1529763567-13131-1-git-send-email-tdas@codeaurora.org> <1529763567-13131-4-git-send-email-tdas@codeaurora.org> <153109408562.143105.15954380130353645468@swboyd.mtv.corp.google.com> <10f87216-caa2-d523-e134-6cf3acd268a7@codeaurora.org> <153111701079.143105.13387458941681113476@swboyd.mtv.corp.google.com> <436cc6a3-7406-c695-7879-3b9d042262cc@codeaurora.org> <153112184177.143105.15452587215679149679@swboyd.mtv.corp.google.com> <288770be-a763-b287-f62a-72ab7616efdb@codeaurora.org> <153114876561.143105.465317097490450694@swboyd.mtv.corp.google.com> Message-ID: <153142449680.48062.13809855257701591509@swboyd.mtv.corp.google.com> User-Agent: alot/0.7 Subject: Re: [PATCH v3 3/3] clk: qcom: Add display clock controller driver for SDM845 Date: Thu, 12 Jul 2018 12:41:36 -0700 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Taniya Das (2018-07-12 10:21:33) > ++ Display driver team, > = > On 7/9/2018 8:36 PM, Stephen Boyd wrote: > > Quoting Taniya Das (2018-07-09 02:34:07) > >> > >> > >> On 7/9/2018 1:07 PM, Stephen Boyd wrote: > >>> Quoting Taniya Das (2018-07-09 00:07:21) > >>>> > >>>> > >>>> On 7/9/2018 11:46 AM, Stephen Boyd wrote: > >>>>>> > >>>>>> > Why is the nocache flag needed? Applies to all clks in this = file. > >>>>>> > > >>>>>> > >>>>>> This flag is required for all RCGs whose PLLs are controlled outsi= de the > >>>>>> clock controller. The display code would require the recalculated = rate > >>>>>> always. > >>>>> > >>>>> Right. Why is the PLL controlled outside of the clock controller? T= he > >>>>> rate should propagate upward to the PLL from here, so who's going > >>>>> outside of that? > >>>>> > >>>> The DSI0/1 PLL are not part of the display clock controller, but in = the > >>>> display subsystem which are managed by the DRM drivers. When DRM dri= vers > >>>> query for the rate clock driver should always return the non cached = rates. > >>> > >>> Why? Is the DSI PLL changing rate all the time, randomly, without goi= ng > >>> through the clk APIs to do so? > >>> > >> > >> Hmm, I am afraid I do not have an answer for this, but this was the > >> requirement to always return the non cached rates from the clock drive= r. > >> > > = > > Ok. Who knows about this requirement? Can we add someone from the > > display driver to understand more? > > = > As per my discussions offline with the display teams, > = > There is a use-case where the clock framework is unaware of the PLL VCO = > frequency change and thus the drivers would query to get the actual HW = > frequency rather than the cached one. > = > Do you think keeping these flags would have any impact other than always = > getting the non-cached rates? > = The flag will make it so clk_get_rate() works in spite of something changing the frequency behind the framework's back, but I want to understand what and why it's changing without framework involvement. We shouldn't need the flag here, because this flag is typically for clks that are controlled by some other entity that the kernel doesn't have control over. In this case, it seems like we have full control of the clk tree for the display PLL down to this clk, so it should be perfectly fine to not have this flag. The presence of the flag means that the display driver is doing something wrong.