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[172.10.233.147]) by smtp.gmail.com with ESMTPSA id u64-v6sm4799433ywu.107.2018.07.14.12.58.14 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 14 Jul 2018 12:58:16 -0700 (PDT) Date: Sat, 14 Jul 2018 12:58:07 -0700 (PDT) From: Hugh Dickins X-X-Sender: hugh@eggly.anvils To: Ingo Molnar cc: Thomas Gleixner , "Metzger, Markus T" , Peter Zijlstra , Arnaldo Carvalho de Melo , "Shishkin, Alexander" , "Kleen, Andi" , "Hansen, Dave" , Stephane Eranian , linux-kernel@vger.kernel.org, x86@kernel.org Subject: [PATCH] x86/events/intel/ds: Fix bts_interrupt_threshold alignment In-Reply-To: Message-ID: References: User-Agent: Alpine 2.11 (LSU 23 2013-08-11) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Markus reported that BTS is sporadically missing the tail of the trace in the perf_event data buffer: [decode error (1): instruction overflow] shown in GDB; and bisected it to the conversion of debug_store to PTI. A little "optimization" crept into alloc_bts_buffer(), which mistakenly placed bts_interrupt_threshold away from the 24-byte record boundary. Intel SDM Vol 3B 17.4.9 says "This address must point to an offset from the BTS buffer base that is a multiple of the BTS record size." Revert "max" from a byte count to a record count, to calculate the bts_interrupt_threshold correctly: which turns out to fix problem seen. Fixes: c1961a4631da ("x86/events/intel/ds: Map debug buffers in cpu_entry_area") Signed-off-by: Hugh Dickins Reported-and-tested-by: Markus T Metzger Cc: # v4.14+ --- Sorry for the spam: I missed out [PATCH] and x86@kernel.org yesterday. arch/x86/events/intel/ds.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) --- 4.18-rc4/arch/x86/events/intel/ds.c 2018-06-03 14:15:21.000000000 -0700 +++ linux/arch/x86/events/intel/ds.c 2018-07-12 17:38:28.471378616 -0700 @@ -408,9 +408,11 @@ static int alloc_bts_buffer(int cpu) ds->bts_buffer_base = (unsigned long) cea; ds_update_cea(cea, buffer, BTS_BUFFER_SIZE, PAGE_KERNEL); ds->bts_index = ds->bts_buffer_base; - max = BTS_RECORD_SIZE * (BTS_BUFFER_SIZE / BTS_RECORD_SIZE); - ds->bts_absolute_maximum = ds->bts_buffer_base + max; - ds->bts_interrupt_threshold = ds->bts_absolute_maximum - (max / 16); + max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE; + ds->bts_absolute_maximum = ds->bts_buffer_base + + max * BTS_RECORD_SIZE; + ds->bts_interrupt_threshold = ds->bts_absolute_maximum - + (max / 16) * BTS_RECORD_SIZE; return 0; }