Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Subject: Re: [PATCH RESEND] drm/meson: Make DMT timings parameters and pixel
 clock generic
To:     Jerome Brunet <jbrunet@baylibre.com>,
        dri-devel@lists.freedesktop.org
Cc:     linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org
References: <1531726814-14638-1-git-send-email-narmstrong@baylibre.com>
 <1531730163.12853.10.camel@baylibre.com>
From:   Neil Armstrong <narmstrong@baylibre.com>
Openpgp: preference=signencrypt
Autocrypt: addr=narmstrong@baylibre.com; prefer-encrypt=mutual; keydata=
 xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP
 GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4
 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9
 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik
 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB
 AAHNKE5laWwgQXJtc3Ryb25nIDxuYXJtc3Ryb25nQGJheWxpYnJlLmNvbT7CwHsEEwEKACUC
 GyMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheABQJXDO2CAhkBAAoJEBaat7Gkz/iubGIH/iyk
 RqvgB62oKOFlgOTYCMkYpm2aAOZZLf6VKHKc7DoVwuUkjHfIRXdslbrxi4pk5VKU6ZP9AKsN
 NtMZntB8WrBTtkAZfZbTF7850uwd3eU5cN/7N1Q6g0JQihE7w4GlIkEpQ8vwSg5W7hkx3yQ6
 2YzrUZh/b7QThXbNZ7xOeSEms014QXazx8+txR7jrGF3dYxBsCkotO/8DNtZ1R+aUvRfpKg5
 ZgABTC0LmAQnuUUf2PHcKFAHZo5KrdO+tyfL+LgTUXIXkK+tenkLsAJ0cagz1EZ5gntuheLD
 YJuzS4zN+1Asmb9kVKxhjSQOcIh6g2tw7vaYJgL/OzJtZi6JlIXOwE0ETVkGzwEIALyKDN/O
 GURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYpQTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXM
 coJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hi
 SvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY4yG6xI99NIPEVE9lNBXBKIlewIyVlkOa
 YvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoMMtsyw18YoX9BqMFInxqYQQ3j/HpVgTSv
 mo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUXoUk33HEAEQEAAcLAXwQYAQIACQUCTVkG
 zwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfnM7IbRuiSZS1unlySUVYu3SD6YBYnNi3G
 5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa33eDIHu/zr1HMKErm+2SD6PO9umRef8V8
 2o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCSKmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+
 RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJ
 C3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTTQbM0WUIBIcGmq38+OgUsMYu4NzLu7uZF
 Acmp6h8g
Organization: Baylibre
Message-ID: <ca08e095-2e7b-58b8-e5cf-db44fe67280b@baylibre.com>
Date:   Mon, 16 Jul 2018 11:18:08 +0200
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101
 Thunderbird/52.9.1
MIME-Version: 1.0
In-Reply-To: <1531730163.12853.10.camel@baylibre.com>
Content-Type: text/plain; charset=utf-8
Content-Language: en-US
Content-Transfer-Encoding: 7bit
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

On 16/07/2018 10:36, Jerome Brunet wrote:
> On Mon, 2018-07-16 at 09:40 +0200, Neil Armstrong wrote:
>> Remove the modes timings tables for DMT modes and calculate the HW
>> paremeters from the modes timings.
>>
>> Switch the DMT modes pixel clock calculation out of the static frequency
>> list to a generic calculation from a range of possible PLL dividers.
>>
>> This patch is an intermediate step towards usage of the Common Clock
>> Framwework for PLL setup, by reworking the code to have common
>> sel_pll() function called by the CEA (HDMI) freq setup and the generic
>> DMT frequencies setup, we should be able to simply call clk_set_rate()
>> on the PLL clock handle in a near future.
>>
>> The CEA (HDMI) and CVBS modes needs very specific clock paths that CCF will
>> never be able to determine by itself, so there is still some work to do for
>> a full handoff to CCF handling the clocks.
> 
> Patch seems to be a good step forward making the display compatible with CCF
> indeed. While full automatic handling through CCF might not possible, it would
> be good if, someday,  we could handle the SoC quirks in CCF, removing the need
> check is the SoC is gxbb, gxl or gxm while setting the clocks.
> 
> If the display driver needs a detailed control over the clock setup, maybe we
> could solve the problem by exporting the intermediate clock elements in CCF
> (such as muxes, ODs, etc...) and let the display driver claim them all ?
> 
> Anyway, the situation is improving so:
> Acked-by: Jerome Brunet <jbrunet@baylibre.com>
> 
>>
>> This setup permits setting non-CEA modes like :
>> - 1600x900-60Hz
>> - 1280x1024-75Hz
>> - 1280x1024-60Hz
>> - 1440x900-60Hz
>> - 1366x768-60Hz
>> - 1280x800-60Hz
>> - 1152x864-75Hz
>> - 1024x768-75Hz
>> - 1024x768-70Hz
>> - 1024x768-60Hz
>> - 832x624-75Hz
>> - 800x600-75Hz
>> - 800x600-72Hz
>> - 800x600-60Hz
>> - 640x480-75Hz
>> - 640x480-73Hz
>> - 640x480-67Hz
>>
>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>> ---
>>  drivers/gpu/drm/meson/meson_dw_hdmi.c |  22 +-
>>  drivers/gpu/drm/meson/meson_vclk.c    | 672 +++++++++++++++-------------------
>>  drivers/gpu/drm/meson/meson_vclk.h    |   4 +
>>  drivers/gpu/drm/meson/meson_venc.c    | 377 +++----------------
>>  drivers/gpu/drm/meson/meson_venc.h    |   3 +-
>>  5 files changed, 358 insertions(+), 720 deletions(-)
>>
[...]


Applied to drm-misc-next with some trivial checkpatch fixes.