Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp3465160imm; Tue, 17 Jul 2018 05:25:29 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcZMfTt8Qxx2h+m6nI56jgiqts8ikSaNe8c4N1JyT+YFVP9qn/WL2xwHqsnoChABlGA1ogA X-Received: by 2002:a17:902:9693:: with SMTP id n19-v6mr1450939plp.212.1531830329479; Tue, 17 Jul 2018 05:25:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531830329; cv=none; d=google.com; s=arc-20160816; b=wJjW4/9PS/WTvZ+Wt9wisEPzqZVGPpn0xPohfIVbt98np02hGwTWBeT8GWEY7TstTg ELaEjw/rpL3HwuibTrPNrGSq26k1SShHfbHz0QJ2zL5r+cfNRhUSuCHC4W8QyJNnnAj2 qfKoS/JdBCBdYADMc1VwczurKBVOOHfpLemrX7HNvlr/YuTX39+KyyQt13tKWC32HIJu 7uXao/JQI/yqd3x5VF0LugLQ8jLoxjGLfn92pLm3TunfzTu1w7xQtVOC3nc8uUXLCQfz 6XPwxEW2eGSdujZjadwxoYTHlfHO502tljsMNPVK+bos2ZnnMOEp+8nHyr44hWTnGLDC Ga/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :organization:references:in-reply-to:date:cc:to:from:subject :message-id:arc-authentication-results; bh=QyK/Fs1ot8kUnNgD8ERM4cBMPiQiD5I6VE0ZzkVVblQ=; b=gNYht+kG6L7F1/l6qD5wkZvnNOArGRpHsrwl3Y/9TDokP/wT1mElf6hImX627GdK9r zUvIwFj87MFroTk9yRQQVSvAMU/68zkMN2tso1swHxM+Jf1cmqS0lm5iXqp/2vTmJTDA 9ajtzyWYLNdAB9mybgqsZCFh/gJezwXCbZoRoL2q3xEHiFwJuNgJ7/eSrufuEe+bR2Fh Q+pyOjHRd9wuLcBxEl0+PPqX/4p7Vg8NdbkEAHk0wb+DKqgxBtPbtlJQI6IKcr6ioinZ M49ntz+Jt4//t5rySZyFLIomztm/b3dykktPBJo4e/wq2MxsUsVd6SbeCohapMVMUuvu 3drg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c18-v6si674720pgh.530.2018.07.17.05.25.14; Tue, 17 Jul 2018 05:25:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731570AbeGQM4D (ORCPT + 99 others); Tue, 17 Jul 2018 08:56:03 -0400 Received: from mga04.intel.com ([192.55.52.120]:42597 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731390AbeGQM4C (ORCPT ); Tue, 17 Jul 2018 08:56:02 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Jul 2018 05:23:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,365,1526367600"; d="scan'208";a="57148805" Received: from smile.fi.intel.com (HELO smile) ([10.237.72.86]) by orsmga007.jf.intel.com with ESMTP; 17 Jul 2018 05:23:35 -0700 Message-ID: Subject: Re: [PATCH 2/2] i2c: designware: Add support for a bus clock From: Andy Shevchenko To: Simon Horman , Phil Edworthy Cc: Jarkko Nikula , Geert Uytterhoeven , linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Mika Westerberg Date: Tue, 17 Jul 2018 15:23:35 +0300 In-Reply-To: <20180717120737.bipotpki3yhn6klf@verge.net.au> References: <1531731553-22979-1-git-send-email-phil.edworthy@renesas.com> <1531731553-22979-3-git-send-email-phil.edworthy@renesas.com> <20180717120737.bipotpki3yhn6klf@verge.net.au> Organization: Intel Finland Oy Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.1-2 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2018-07-17 at 14:07 +0200, Simon Horman wrote: > On Mon, Jul 16, 2018 at 09:59:13AM +0100, Phil Edworthy wrote: > > The Synopsys I2C Controller has a bus clock, but typically SoCs hide > > this away. > > However, on some SoCs you need to explicity enable the bus clock in > > order to > > access the registers. > > Therefore, enable an optional bus clock specified by DT. > > + /* Optional bus clock */ > > + if (!IS_ERR(dev->busclk)) { > > I suspect that error values stored in dev->busclk, other than > -ENOENT, > should be treated as errors. While your point sounds valid (don't remember how clk_get() is implemented), NULL is also OK to have. -- Andy Shevchenko Intel Finland Oy