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[209.132.180.67]) by mx.google.com with ESMTP id q7-v6si682133pll.445.2018.07.17.05.42.59; Tue, 17 Jul 2018 05:43:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=CInMWVXn; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731524AbeGQNOF (ORCPT + 99 others); Tue, 17 Jul 2018 09:14:05 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:39731 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731213AbeGQNOF (ORCPT ); Tue, 17 Jul 2018 09:14:05 -0400 Received: by mail-wr1-f68.google.com with SMTP id h10-v6so1116042wre.6 for ; Tue, 17 Jul 2018 05:41:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=FzdrUWz9VjdE4NgXCJFxMRCriZeOEmexdblLyrGAMDM=; b=CInMWVXn0SmWu0OodOH/CeFkkr634uADEajoacxQyf2KPOjmPNYlhv1vNrtGs+j/Zg ivaZyysd/JOF2Dcp7W51sF7B9VKj/FQR9nHUHikbi5t8L0pzWt3fsYRaZw43z9VJdTnv mr72sZhf38/SGvlnielUthspcHPYL0O6Zej/Z5bD32Conaaga8sx/4o000PUSOsst/zy p2AcmHonTYdhfrw8Kq8LpTw4InNn5aI0Ctmhxqwvk4oTWPaWHktqC3iYYMTTOXVZ476D GRM+zPHkZPI79NGPfPoGYuV/DfHVlOHPDw7H82WO3NJs4FDuFikdr4l30ROfjoPhiQ7i kRag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=FzdrUWz9VjdE4NgXCJFxMRCriZeOEmexdblLyrGAMDM=; b=LYpXXHlcts0BhYVlLbN0y9LkeTaDzt3moPHniQFYAWvpF3OQfgVOfssVHT8O991CwS fjCghUIkeWEYmBL8+9MGfT2vNWgDOSw9LkE54OgBuFsQmrYkEZ6FsZllcA1eTaTihQ6N u8+siFAtz/mMw9jmnF5x8ctYVP6qRugMewVEITaVR2U91hsPk6ofRLIIc8LPaB4Ojsg3 GZSDIdUck2Z0sgf7avqO2jkEdHjABFpK7IIFTNUxYWnBjHO1d36Kn2PKdR9f/g2I21HQ tZNrHzOVmbJND60UKpp1kEu4/J1TalL7swcIpbLf9ZPdubBtateNVfVRVArX3GLUsOrl JKJQ== X-Gm-Message-State: AOUpUlEGmxZ7Z7F6gj3oYvLak8vJSEApt6lEx7mH08sBTRN2HsNNUCfH YdrJdp29GYvU0ihy/v6Y949Bq/elukgLyg0LgVQ= X-Received: by 2002:adf:c891:: with SMTP id k17-v6mr1374124wrh.6.1531831295502; Tue, 17 Jul 2018 05:41:35 -0700 (PDT) MIME-Version: 1.0 References: <20180717085230.17472-1-paul.kocialkowski@bootlin.com> <20180717085230.17472-2-paul.kocialkowski@bootlin.com> In-Reply-To: <20180717085230.17472-2-paul.kocialkowski@bootlin.com> From: Julian Calaby Date: Tue, 17 Jul 2018 22:41:20 +1000 Message-ID: Subject: Re: [linux-sunxi] [PATCH 2/2] drm/sun4i: sun4i: Introduce a quirk for lowest plane alpha support To: paul.kocialkowski@bootlin.com Cc: dri-devel , "Mailing List, Arm" , "linux-kernel@vger.kernel.org" , Maxime Ripard , David Airlie , Chen-Yu Tsai , thomas.petazzoni@bootlin.com, linux-sunxi Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Paul, On Tue, Jul 17, 2018 at 6:53 PM Paul Kocialkowski wrote: > > Not all sunxi platforms with the first version of the Display Engine > support an alpha component on the plane with the lowest z position > (as in: lowest z-pos), that gets blended with the background color. > > In particular, the A13 is known to have this limitation. However, it was > recently discovered that the A20 and A33 are capable of having alpha on > their lowest plane. > > Thus, this introduces a specific quirk to indicate such support, > per-platform. Since this was not tested on sun4i and sun6i platforms, a > conservative approach is kept and this feature is not supported. > > Signed-off-by: Paul Kocialkowski > --- > drivers/gpu/drm/sun4i/sun4i_backend.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c > index a3cc398d4d80..cdc4a8a91ea2 100644 > --- a/drivers/gpu/drm/sun4i/sun4i_backend.c > +++ b/drivers/gpu/drm/sun4i/sun4i_backend.c > @@ -584,8 +587,9 @@ static int sun4i_backend_atomic_check(struct sunxi_engine *engine, > } > > /* We can't have an alpha plane at the lowest position */ > - if (plane_states[0]->fb->format->has_alpha || > - (plane_states[0]->alpha != DRM_BLEND_ALPHA_OPAQUE)) > + if ((plane_states[0]->fb->format->has_alpha || > + (plane_states[0]->alpha != DRM_BLEND_ALPHA_OPAQUE)) && > + !backend->quirks->supports_lowest_plane_alpha) From a readability perspective, it'd be fractionally nicer if the quirk check was before the alpha checks. Thanks, -- Julian Calaby Email: julian.calaby@gmail.com Profile: http://www.google.com/profiles/julian.calaby/