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[209.132.180.67]) by mx.google.com with ESMTP id v14-v6si907761pga.270.2018.07.17.07.24.02; Tue, 17 Jul 2018 07:24:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=tKCM8tqo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731902AbeGQOzP (ORCPT + 99 others); Tue, 17 Jul 2018 10:55:15 -0400 Received: from mail.kernel.org ([198.145.29.99]:34366 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729621AbeGQOzP (ORCPT ); Tue, 17 Jul 2018 10:55:15 -0400 Received: from mail-it0-f50.google.com (mail-it0-f50.google.com [209.85.214.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B13C921476; Tue, 17 Jul 2018 14:22:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1531837340; bh=tH1TrPtS9VLFrWAvJbTOk+nHJahZHNs/5EH8WN/2NJw=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=tKCM8tqoObmICYnc+kiWX1udWizv++/BYLQcnuJkKS9B+ieKV/npJ2F3az+ISz4Xp BTwRy+79Y7cbH9JFQd4L7DGttui/rcg+Aa0Lw8VuG5Ju+CxRo2aSKXYhlk9YDbquvJ QMY6+MAyjp1UgR2kZtgMhZEuv+LQdbaX0qfUtNB8= Received: by mail-it0-f50.google.com with SMTP id 72-v6so2043137itw.3; Tue, 17 Jul 2018 07:22:20 -0700 (PDT) X-Gm-Message-State: AOUpUlE6Zi6dgKMefkPVA7QaDMf3tVB0X2QMkUTRHWCBxLdsHyNPwYRw WnBgY6be7xS+nzoHSHViNouJZDbRLgYmYuI6bg== X-Received: by 2002:a02:9936:: with SMTP id r51-v6mr1696009jaj.46.1531837340200; Tue, 17 Jul 2018 07:22:20 -0700 (PDT) MIME-Version: 1.0 References: <1531396813-6581-1-git-send-email-avienamo@nvidia.com> <1531396813-6581-6-git-send-email-avienamo@nvidia.com> <20180716154309.GA16477@rob-hp-laptop> <20180717152318.3608e3f9@dhcp-10-21-25-168> In-Reply-To: <20180717152318.3608e3f9@dhcp-10-21-25-168> From: Rob Herring Date: Tue, 17 Jul 2018 08:22:07 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 5/7] dt-bindings: Add Tegra PMC pad configuration bindings To: Aapo Vienamo Cc: Mark Rutland , Thierry Reding , Jon Hunter , Mikko Perttunen , Laxman Dewangan , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jul 17, 2018 at 6:23 AM Aapo Vienamo wrote: > > On Mon, 16 Jul 2018 09:43:09 -0600 > Rob Herring wrote: > > > On Thu, Jul 12, 2018 at 03:00:11PM +0300, Aapo Vienamo wrote: > > > Document the pinctrl bindings used by the PMC driver for performing pad > > > configuration. Both nvidia,tegra186-pmc.txt and nvidia,tegra20-pmc.txt > > > are modified as they both cover SoC generations for which these bindings > > > apply. > > > > > > Add a header defining Tegra PMC pad voltage configurations. > > > > > > Signed-off-by: Aapo Vienamo > > > Acked-by: Jon Hunter > > > --- > > > .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 84 +++++++++++++++++++ > > > .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 95 ++++++++++++++++++++++ > > > include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h | 18 ++++ > > > 3 files changed, 197 insertions(+) > > > create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h > > > > > > diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt > > > index 5a3bf7c..9528f41 100644 > > > --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt > > > +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt > > > @@ -34,3 +34,87 @@ Board DTS: > > > pmc@c360000 { > > > nvidia,invert-interrupt; > > > }; > > > + > > > +== Pad Control Nodes == > > > + > > > +The PMC can be used to set pad power state and voltage configuration. > > > +The pad configuration is done via the pinctrl framework. The driver > > > +implements power-source, low-power-enable, and low-power-disable pinconf > > > +pin configuration node properties. Each pinctrl pin corresponds to a > > > +single Tegra PMC pad. Thus, in the following sections of this document > > > +pin refers to the pinctrl frameworks notion of a Tegra PMC pad. > > > > "pinctrl framework" is Linux specific and doesn't belong in the binding. > > Neither does what a driver supports. Describe what the h/w supports. > > > > > + > > > +The pad configuration state nodes are placed under the pmc node and they > > > +are referred to by the pinctrl client device properties. For more > > > > Another driver detail not relevant. > > > > > +information see the examples presented later and > > > > examples don't document bindings. The documentation should be complete > > without examples. > > > > > +Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. > > > + > > > +The values accepted by power-source property are > > > +TEGRA_IO_PAD_VOLTAGE_1V8 and TEGRA_IO_PAD_VOLTAGE_3V3, which are defined > > > +in dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. > > > > You need to list out what properties the child nodes can have. > > > > power-source needs a vendor prefix. > > Isn't it a generic pinctrl property? I don't know offhand. Doesn't look like it if you have custom values. Rob