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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 17 Jul 2018 15:37:45 -0400 Received: from b01ledav003.gho.pok.ibm.com (b01ledav003.gho.pok.ibm.com [9.57.199.108]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w6HJbjIm6750490 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 17 Jul 2018 19:37:45 GMT Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6E17CB206A; Tue, 17 Jul 2018 15:37:36 -0400 (EDT) Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4F3A9B2066; Tue, 17 Jul 2018 15:37:36 -0400 (EDT) Received: from paulmck-ThinkPad-W541 (unknown [9.70.82.159]) by b01ledav003.gho.pok.ibm.com (Postfix) with ESMTP; Tue, 17 Jul 2018 15:37:36 -0400 (EDT) Received: by paulmck-ThinkPad-W541 (Postfix, from userid 1000) id 4AB2616C86E1; Tue, 17 Jul 2018 12:40:09 -0700 (PDT) Date: Tue, 17 Jul 2018 12:40:09 -0700 From: "Paul E. McKenney" To: Peter Zijlstra Cc: Linus Torvalds , Michael Ellerman , Alan Stern , andrea.parri@amarulasolutions.com, Will Deacon , Akira Yokosawa , Boqun Feng , Daniel Lustig , David Howells , Jade Alglave , Luc Maranget , Nick Piggin , Linux Kernel Mailing List Subject: Re: [PATCH v2] tools/memory-model: Add extra ordering for locks and remove it for ordinary release/acquire Reply-To: paulmck@linux.vnet.ibm.com References: <20180713110851.GY2494@hirez.programming.kicks-ass.net> <87tvp3xonl.fsf@concordia.ellerman.id.au> <20180713164239.GZ2494@hirez.programming.kicks-ass.net> <87601fz1kc.fsf@concordia.ellerman.id.au> <87va9dyl8y.fsf@concordia.ellerman.id.au> <20180717183341.GQ12945@linux.vnet.ibm.com> <20180717184255.GM2494@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180717184255.GM2494@hirez.programming.kicks-ass.net> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-GCONF: 00 x-cbid: 18071719-0068-0000-0000-00000319919C X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00009381; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000266; SDB=6.01062227; UDB=6.00545367; IPR=6.00840084; MB=3.00022174; MTD=3.00000008; XFM=3.00000015; UTC=2018-07-17 19:37:49 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18071719-0069-0000-0000-00004510EF59 Message-Id: <20180717194009.GT12945@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-07-17_05:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=422 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1806210000 definitions=main-1807170203 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jul 17, 2018 at 08:42:55PM +0200, Peter Zijlstra wrote: > On Tue, Jul 17, 2018 at 11:33:41AM -0700, Paul E. McKenney wrote: > > On Tue, Jul 17, 2018 at 09:19:15AM -0700, Linus Torvalds wrote: > > > > > > In particular, I find: > > > > > > "isync is not a memory barrier instruction, but the > > > load-compare-conditional branch-isync sequence can provide this > > > ordering property" > > > > > > so why are you doing "sync/lwsync", when it sounds like "isync/lwsync" > > > (for lock/unlock) is the right thing and would already give memory > > > barrier semantics? > > > > The PowerPC guys will correct me if I miss something here... > > > > The isync provides ordering roughly similar to lwsync, but nowhere near > > as strong as sync, and it is sync that would be needed to cause lock > > acquisition to provide full ordering. The reason for using lwsync instead > > of isync is that the former proved to be faster on recent hardware. > > The reason that the kernel still has the ability to instead generate > > isync instructions is that some older PowerPC hardware does not provide > > the lwsync instruction. If the hardware does support lwsync, the isync > > instructions are overwritten with lwsync at boot time. > > Isn't ISYNC the instruction-sync pipeline flush instruction? That is > used as an smp_rmb() here to, together with the control dependency from the > LL/SC, to form a LOAD->{LOAD,STORE} (aka LOAD-ACQUIRE) ordering? That is the one! > Where LWSYNC provides a TSO like ordering and SYNC provides a full > transitive barrier aka. smp_mb() (althgouh I think it is strictly > stronger than smp_mb() since it also implies completion, which smp_mb() > does not). > > And since both LL/SC-CTRL + ISYNC / LWSYNC are strictly CPU local, they > cannot be used to create RCsc ordering. Completely agreed, there needs to be a sync instruction in either the lock or the unlock to get RCsc ordering. Neither lwsync nor isync can provide the needed ordering. Thanx, Paul