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McKenney" Cc: Linus Torvalds , Michael Ellerman , Peter Zijlstra , Alan Stern , Will Deacon , Akira Yokosawa , Boqun Feng , Daniel Lustig , David Howells , Jade Alglave , Luc Maranget , Nick Piggin , Linux Kernel Mailing List Subject: Re: [PATCH v2] tools/memory-model: Add extra ordering for locks and remove it for ordinary release/acquire Message-ID: <20180717194001.GA3781@andrea> References: <20180712180511.GP2476@hirez.programming.kicks-ass.net> <20180713110851.GY2494@hirez.programming.kicks-ass.net> <87tvp3xonl.fsf@concordia.ellerman.id.au> <20180713164239.GZ2494@hirez.programming.kicks-ass.net> <87601fz1kc.fsf@concordia.ellerman.id.au> <87va9dyl8y.fsf@concordia.ellerman.id.au> <20180717183341.GQ12945@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180717183341.GQ12945@linux.vnet.ibm.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > That said, I don't understand the powerpc memory ordering. I thought > > the rules were "isync on lock, lwsync on unlock". > > > > That's what the AIX docs imply, at least. > > > > In particular, I find: > > > > "isync is not a memory barrier instruction, but the > > load-compare-conditional branch-isync sequence can provide this > > ordering property" > > > > so why are you doing "sync/lwsync", when it sounds like "isync/lwsync" > > (for lock/unlock) is the right thing and would already give memory > > barrier semantics? > > The PowerPC guys will correct me if I miss something here... [Same here.] > > The isync provides ordering roughly similar to lwsync, but nowhere near > as strong as sync, and it is sync that would be needed to cause lock > acquisition to provide full ordering. IIRC, ctrl+isync is even *weaker* than lwsync in certain respects, e.g., the former doesn't provide A-cumulativity according to the architectural intent. >The reason for using lwsync instead > of isync is that the former proved to be faster on recent hardware. Interesting; can you add some references about this? Andrea > The reason that the kernel still has the ability to instead generate > isync instructions is that some older PowerPC hardware does not provide > the lwsync instruction. If the hardware does support lwsync, the isync > instructions are overwritten with lwsync at boot time. > > Thanx, Paul >