Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp57574imm; Tue, 17 Jul 2018 20:43:56 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeG6FzIw7zUmFOG1PYrCQ/jK77PujsaclzRje37F0T52runDD/zWx+xHbJXO+YOJFrkDi9I X-Received: by 2002:a17:902:1703:: with SMTP id i3-v6mr4132048pli.263.1531885436029; Tue, 17 Jul 2018 20:43:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531885436; cv=none; d=google.com; s=arc-20160816; b=Y6cwotnsyCExCl3RT+zdlino9A8uuVSqd18jlbFiHlXc/piqWi27rCs/Ojn39geBY5 oXJ7G2UW++KcZeN7WzZJPjyZq5ovw5mhTTv0gQwq8OvEgWXASa2JsGK8VlntJxvEfHVD Tj+Iax4VImSDukNpwxCQhgBihG0wPjaX2hNddHCkyJcg5QXlCP4ai84N+W3WwyxiwpeC qjWVK3M6CUgsReXY0oPWALEbeQ1vriiRXWX0myb9OPSlMb5+/vkixjl0SUQPwOVi0KWw aa6FQFysx2q8EcbKGW6e16+sZgnAjRhhLXGfFuqqJ2Z0dwOcwem8eSOZ2+PM4gnFPQvN M8Bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:dkim-signature :arc-authentication-results; bh=8eq+pE3RnleQrlqpjqeP5iGQjAeunhaEwy6aXm7zaHw=; b=A4DULdkwLq34kM7cmSIm658/5d8m12t5jA7Q4ufpbciMGboeG4pJSWfjv1tn8eMufN DBqOYQnijmbUHbpIVXhvBjENEuVNp116olUdmPA1gp0IKbcicDgkbbFHfAai+3YMtj2K Ps+FUc0J+gY/unX6MYv99f8+lqfzNSpS3GBzJ/86I05WKMs/xMcDsVeqyxx33+mQIH7h kA6kpHW8ZVmr/AS6hrJ/VmjK285t0+HZpQyosy9SFli20iOiyG4NAiHREObAB4pW0qiJ bN6m9U4Iyc8BarGVLVGDk/0W6u64FZFT8ziasvyynV5jpnzrB2d3NMjMuFW1i6CnPIRx 5knQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FIu2wHPR; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 194-v6si2686427pfz.101.2018.07.17.20.43.39; Tue, 17 Jul 2018 20:43:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FIu2wHPR; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726317AbeGRESt (ORCPT + 99 others); Wed, 18 Jul 2018 00:18:49 -0400 Received: from mail-qk0-f196.google.com ([209.85.220.196]:36937 "EHLO mail-qk0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726138AbeGRESt (ORCPT ); Wed, 18 Jul 2018 00:18:49 -0400 Received: by mail-qk0-f196.google.com with SMTP id t79-v6so1705719qke.4 for ; Tue, 17 Jul 2018 20:43:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=8eq+pE3RnleQrlqpjqeP5iGQjAeunhaEwy6aXm7zaHw=; b=FIu2wHPRru/DaDhipsXdaSW0jd6V4UZaajuKz19Ccw1Bwk5THpNx1bu8qaRnpa1dAK Y57H2M66RZ53+U9Gt/g2el03gVB73Zyxo3Utgt91D5moE7CxI+STStXnAQ9JWFYhxt/d w86Szp76eD4+4YIir7bufTfkcvjdduAoKWbck= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=8eq+pE3RnleQrlqpjqeP5iGQjAeunhaEwy6aXm7zaHw=; b=kmYj59jqH/NsfrLR3037daqCHKDyCy22VMVA6i1ZJA79+/EE0p51nZFONaA3CFf9rR DBUIHH1UwfAQ47Wui/SkWdvNVAe2+bApTwh9e1rFisRMkKPI7+dCT7uWUwuJ4Mcc8Ya0 kN+8CNj7n7arcGSAeA8OxIAgalWE/GelgH8kmPKFPYCjkFDmIBJvBRAXBR47A40Ht6/m qRC5efDtq/Udx2y5oM0z5LiRLeG2K6WLlIIpQm6uJh5HkFiW2Y6yhsoHF+rLKRCG/GZy WhuamQQdgbPSgdatYtVign83vTvn58HeYnhqKh7XYrQHrRfWT5bglfm5bivGgGdcASn0 BSIg== X-Gm-Message-State: AOUpUlEH8uzAbbPpcnVY3Qtv4z83BhCdAVuVB30zmaURs31hD1xaXYO0 BtItvaMfu7SbFmnRGa8qySZGGUf9J8B43tXzlichiScL X-Received: by 2002:a37:9187:: with SMTP id t129-v6mr3874142qkd.112.1531885382247; Tue, 17 Jul 2018 20:43:02 -0700 (PDT) MIME-Version: 1.0 References: <8f833fee80565c4dfd381697e47f99fb5f9e65d3.1531384019.git.amit.kucheria@linaro.org> <20180717232907.GC129942@google.com> In-Reply-To: <20180717232907.GC129942@google.com> From: Amit Kucheria Date: Wed, 18 Jul 2018 09:12:50 +0530 Message-ID: Subject: Re: [PATCH v7 2/7] thermal: tsens: Add support to split up register address space into two To: mka@chromium.org Cc: Linux Kernel Mailing List , Rajendra Nayak , linux-arm-msm , Bjorn Andersson , Eduardo Valentin , smohanad@codeaurora.org, Vivek Gautam , Andy Gross , Doug Anderson , Zhang Rui , Linux PM list Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jul 18, 2018 at 4:59 AM Matthias Kaehlcke wrote: > > On Thu, Jul 12, 2018 at 02:09:03PM +0530, Amit Kucheria wrote: > > There are two banks of registers for v2 TSENS IPs: SROT and TM. On older > > SoCs these were contiguous, leading to DTs mapping them as one register > > address space of size 0x2000. In newer SoCs, these two banks are not > > contiguous anymore. > > > > Add logic to init_common() to differentiate between old and new DTs and > > adjust associated offsets for the TM register bank so that the old DTs will > > continue to function correctly. > > > > Signed-off-by: Amit Kucheria > > Reviewed-by: Bjorn Andersson > > Tested-by: Matthias Kaehlcke > > --- > > drivers/thermal/qcom/tsens-8996.c | 4 ++-- > > drivers/thermal/qcom/tsens-common.c | 12 ++++++++++++ > > drivers/thermal/qcom/tsens.h | 1 + > > 3 files changed, 15 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/thermal/qcom/tsens-8996.c b/drivers/thermal/qcom/tsens-8996.c > > index e1f7781..3e60cec 100644 > > --- a/drivers/thermal/qcom/tsens-8996.c > > +++ b/drivers/thermal/qcom/tsens-8996.c > > @@ -16,7 +16,7 @@ > > #include > > #include "tsens.h" > > > > -#define STATUS_OFFSET 0x10a0 > > +#define STATUS_OFFSET 0xa0 > > #define LAST_TEMP_MASK 0xfff > > #define STATUS_VALID_BIT BIT(21) > > #define CODE_SIGN_BIT BIT(11) > > @@ -28,7 +28,7 @@ static int get_temp_8996(struct tsens_device *tmdev, int id, int *temp) > > unsigned int sensor_addr; > > int last_temp = 0, last_temp2 = 0, last_temp3 = 0, ret; > > > > - sensor_addr = STATUS_OFFSET + s->hw_id * 4; > > + sensor_addr = tmdev->tm_offset + STATUS_OFFSET + s->hw_id * 4; > > ret = regmap_read(tmdev->map, sensor_addr, &code); > > if (ret) > > return ret; > > diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c > > index b1449ad..c22dc18 100644 > > --- a/drivers/thermal/qcom/tsens-common.c > > +++ b/drivers/thermal/qcom/tsens-common.c > > @@ -16,6 +16,7 @@ > > #include > > #include > > #include > > +#include > > #include > > #include > > #include "tsens.h" > > @@ -126,11 +127,22 @@ static const struct regmap_config tsens_config = { > > int __init init_common(struct tsens_device *tmdev) > > { > > void __iomem *base; > > + struct platform_device *op = of_find_device_by_node(tmdev->dev->of_node); > > > > + if (!op) > > + return -EINVAL; > > base = of_iomap(tmdev->dev->of_node, 0); > > if (!base) > > return -EINVAL; > > > > + /* The driver only uses the TM register address space for now */ > > + if (op->num_resources > 1) { > > + tmdev->tm_offset = 0; > > + } else { > > + /* old DTs where SROT and TM were in a contiguous 2K block */ > > + tmdev->tm_offset = 0x1000; > > + } > > nit: no curly braces for conditionals with a single statement. There > is probably no need to respin just for this though. Yeah, that was leftover from refactoring because I have an upcoming patch that adds SROT mapping inside those braces. I'm about to post it soon. > Reviewed-by: Matthias Kaehlcke