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Subject: Re: [PATCH 4/7] x86,tlb: make lazy TLB mode lazier
From:   Andy Lutomirski <luto@amacapital.net>
In-Reply-To: <B6566AA4-2E8A-43BD-A224-0F6D4747B8FB@surriel.com>
Date:   Wed, 18 Jul 2018 13:13:13 -1000
Cc:     Andy Lutomirski <luto@kernel.org>,
        LKML <linux-kernel@vger.kernel.org>, X86 ML <x86@kernel.org>,
        Mike Galbraith <efault@gmx.de>,
        kernel-team <kernel-team@fb.com>, Ingo Molnar <mingo@kernel.org>,
        Dave Hansen <dave.hansen@intel.com>
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Message-Id: <F93A3335-4830-4E36-9179-D0FA5D640C8A@amacapital.net>
References: <20180716190337.26133-1-riel@surriel.com> <20180716190337.26133-5-riel@surriel.com> <CALCETrUMntRe_LYX5wj9YD4xZ+84QExK+ZNb3yxEBDEKa7nePQ@mail.gmail.com> <B6566AA4-2E8A-43BD-A224-0F6D4747B8FB@surriel.com>
To:     Rik van Riel <riel@surriel.com>
Sender: linux-kernel-owner@vger.kernel.org
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> On Jul 18, 2018, at 10:58 AM, Rik van Riel <riel@surriel.com> wrote:
>=20
>=20
>=20
>> On Jul 17, 2018, at 4:04 PM, Andy Lutomirski <luto@kernel.org> wrote:
>>=20
>>=20
>> I think you've introduced a minor-ish performance regression due to
>> changing the old (admittedly terribly documented) control flow a bit.
>> Before, if real_prev =3D=3D next, we would skip:
>>=20
>> load_mm_cr4(next);
>> switch_ldt(real_prev, next);
>>=20
>> Now we don't any more.  I think you should reinstate that
>> optimization.  It's probably as simple as wrapping them in an if
>> (real_priv !=3D next) with a comment like /* Remote changes that would
>> require a cr4 or ldt reload will unconditionally send an IPI even to
>> lazy CPUs.  So, if we aren't changing our mm, we don't need to refresh
>> cr4 or the ldt */
>=20
> Looks like switch_ldt already skips reloading the LDT when prev equals
> next, or when they simply have the same LDT values:
>=20
>        if (unlikely((unsigned long)prev->context.ldt |
>                     (unsigned long)next->context.ldt))
>                load_mm_ldt(next);
>=20

Read that again?  It will reload if there=E2=80=99s an LDT, even if it=E2=80=
=99s the same one.

> It appears that the cr4 bits have a similar optimization:
>=20
> static inline void cr4_set_bits(unsigned long mask)
> {
>        unsigned long cr4, flags;
>=20
>        local_irq_save(flags);
>        cr4 =3D this_cpu_read(cpu_tlbstate.cr4);
>        if ((cr4 | mask) !=3D cr4)
>                __cr4_set(cr4 | mask);
>        local_irq_restore(flags);
> }
>>=20
>> Hmm.  load_mm_cr4() should bypass itself when mm =3D=3D &init_mm.  Want t=
o
>> fix that part or should I?
>>=20
> Looks like there might not be anything to do here, after all.

But if init_mm and the thread that just went idle have different selected cr=
4 values, we=E2=80=99ll still write it.  With your lazy TLB work, it=E2=80=99=
s less of a big deal, but still.

I=E2=80=99m happy to fix this myself, though.

>=20
> On to the lazy TLB mm_struct refcounting stuff :)
>=20

Which refcount?  mm_users shouldn=E2=80=99t be hot, so I assume you=E2=80=99=
re talking about mm_count. My suggestion is to get rid of mm_count instead o=
f trying to optimize it.=