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[209.132.180.67]) by mx.google.com with ESMTP id o189-v6si4605194pga.577.2018.07.18.18.47.02; Wed, 18 Jul 2018 18:47:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731058AbeGSC1H (ORCPT + 99 others); Wed, 18 Jul 2018 22:27:07 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:9651 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729230AbeGSC1H (ORCPT ); Wed, 18 Jul 2018 22:27:07 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 15512BDCD52B6; Thu, 19 Jul 2018 09:46:14 +0800 (CST) Received: from [127.0.0.1] (10.184.52.56) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.382.0; Thu, 19 Jul 2018 09:46:06 +0800 Subject: Re: [PATCH 4/5] crypto: Add IV generation templates To: Milan Broz , Mark Brown CC: , , , , , , References: <1531899055-29362-1-git-send-email-wangxiongfeng2@huawei.com> <1531899055-29362-5-git-send-email-wangxiongfeng2@huawei.com> <20180718164625.GA20360@sirena.org.uk> <82248c13-42fe-b598-0cd7-68e5db0b51be@gmail.com> From: Xiongfeng Wang Message-ID: Date: Thu, 19 Jul 2018 09:46:04 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <82248c13-42fe-b598-0cd7-68e5db0b51be@gmail.com> Content-Type: text/plain; charset="windows-1252" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.184.52.56] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 2018/7/19 1:17, Milan Broz wrote: > On 18/07/18 18:46, Mark Brown wrote: >> On Wed, Jul 18, 2018 at 10:16:05AM +0200, Milan Broz wrote: >> >>> So we are here again and moving INTERNAL dm-crypt functionality into >>> cryptoapi. > (namely TCW and LMK) do much more that IV - they modify encryption mode. > This was a hack to support some FDE encryption modes (old Truecrypt and loopAES) > and that should not spread outside dm-crypt (and blame me for this code hacks :). > > 2) If the reason is performance, please provide numbers with the patch. > What I see now is that the performance is almost the same. So why you are doing it? > Any real hw that benefits from it? I add IV templates, such as 'plain()', 'benbi()' When applying it to the existing algorithm, such as 'aes-cbc', and so on, it generates new algorithm 'aes-cbc-plain', 'aes-cbc-benbi. This patch modify the dm-crypt to rely on the new algorithm 'aes-cbc-benbi'. Dm-crypt passes the whole 'bio' to 'aes-cbc-benbi', rather than divide the bio into sectors, and alternatively pass each sector to 'aes-cbc'. Because the internal implementation of the IV template 'benbi()' is still dividing the whole bio into sectors, so the performance is almost the same. The purpose of this patch is to let dm-crypt rely on the new algorithm 'aes-cbc-benbi' and pass the whole bio to the new algorithm. And then if the hardware driver implements this new algorithm, it can get the data of the bio at one time, and return the processed data at one time. I think it will decrease the overhead of passing each sector alternatively. But the hardware need to implement the new algorithm if it want to benefit from this. Thanks, Xiongfeng > > I added 4k sector support in dmcrypt and IMO this helps much more > than some hw IV accelerations (AFAIK is is already used in some mainframe > accelerators this way because of performance). > > Milan > >