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[209.132.180.67]) by mx.google.com with ESMTP id h36-v6si586348pgm.125.2018.07.19.18.02.56; Thu, 19 Jul 2018 18:03:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Jc4OUwwh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730687AbeGTBsF (ORCPT + 99 others); Thu, 19 Jul 2018 21:48:05 -0400 Received: from mail-io0-f196.google.com ([209.85.223.196]:42962 "EHLO mail-io0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729215AbeGTBsF (ORCPT ); Thu, 19 Jul 2018 21:48:05 -0400 Received: by mail-io0-f196.google.com with SMTP id g11-v6so8632658ioq.9 for ; Thu, 19 Jul 2018 18:02:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=thCmha/x3iDQih8sEVZ1s/JipgEwA3VYYsSrvLe9QKo=; b=Jc4OUwwhCL9y+tHR1pL8mppiCewGmws/OWadx2ADrAT/XZcG9IWqeyEubbAnhL8leH GB85DaolK7a1mWd096Q75sWCzsnOLKzKHLiz2fngIUFEXcVmAoqBprSnVcFpJG5bM8ks JBRf5eHWHIiE2Ukg7z1w6ZOKNiClInQFzml0E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=thCmha/x3iDQih8sEVZ1s/JipgEwA3VYYsSrvLe9QKo=; b=amjykb7cuVZhbgBPDFNMGIWxDS5Y8w35VVPauhDbn3lv5Xa04Hygxez7OWjJkH+55J IpwiBq1Rxj+UWfFm/OFhnEszKwGn6vEkuXXHdF0r097bzhEqDxByE5Js4jRWOKveOhbq qVJk1QVUQbL55mrs9Q2W4iBS9YsAbSMmQ/bqdK8omxqyhz5yU/ULFgvpFba36b0LSTUc Z26DS3TNkf/Ma8W4yYnzktJtSsBMWWLD5dJ6z1s/rc3kc/N92XpzSi6mD+djO2iJyjQ+ ucA1hIpJLhyuSmGfwdboe+vr51gH4HzhkcE9s6f+yhjiRwreI57V7OqTw7Gwrhw4AlTL q/eQ== X-Gm-Message-State: AOUpUlFaS3idpn/Gp8tABLRm/D+1JUo6tu73r9kbpkfdGVW3834T9e7p oZIvGfN3DfuUghHW8/Aztm4BG8YggUAXU4IwiaGE7Q== X-Received: by 2002:a6b:be83:: with SMTP id o125-v6mr10320249iof.173.1532048541992; Thu, 19 Jul 2018 18:02:21 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:ac05:0:0:0:0:0 with HTTP; Thu, 19 Jul 2018 18:02:21 -0700 (PDT) In-Reply-To: <20180719155026.GF27938@sirena.org.uk> References: <1531899055-29362-1-git-send-email-wangxiongfeng2@huawei.com> <5d0bb72c-862e-63be-3cc5-83ed02b9a575@huawei.com> <20180719155026.GF27938@sirena.org.uk> From: Ard Biesheuvel Date: Fri, 20 Jul 2018 10:02:21 +0900 Message-ID: Subject: Re: [PATCH 0/5] crypto: add IV generation templates To: Mark Brown Cc: Xiongfeng Wang , Arnd Bergmann , Alasdair Kergon , Mike Snitzer , Herbert Xu , dm-devel@redhat.com, Linux Kernel Mailing List , Jonathan Cameron Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 20 July 2018 at 00:50, Mark Brown wrote: > On Thu, Jul 19, 2018 at 11:08:52PM +0900, Ard Biesheuvel wrote: > >> But this will only be the case if the accelerator is capable of doing >> the IV generation and en/decryption of multiple contiguous sectors in >> a single call. Otherwise, you are just shifting work from one layer to >> the next. > >> So at this point, it would be useful to clarify what exactly these >> accelerators are doing and how. > > Existing hardware can definitely do the IV generation and I believe that > it can chain multiple sectors together though I'd need to confirm this, > as mentioned elsewhere in the thread the ccree driver is for one of > the relevant devices. I've poked some relevant people. As far as I can infer from the ccree driver source, IV generation and en/decryption are separate operations, and given that each sector requires both operations to be applied in sequence, letting the crypto layer handle an entire bio does not have any benefit *at the moment*. In fact, it seems to me that the ability to use protected AES keys is much more appealing than any performance argument (including 'it may be slower but at least it does not load the CPU'), so some background on how such a change would enable this use case would be beneficial as well to getting this adopted. So my recommendation would be to focus on moving the IV generation into the crypto layer, but conservatively, and not confuse people by making additional changes that could theoretically improve performance, but only on hardware that does not exist. -- Ard.