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[209.132.180.67]) by mx.google.com with ESMTP id bc12-v6si1169426plb.373.2018.07.20.01.13.05; Fri, 20 Jul 2018 01:13:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728094AbeGTI7h (ORCPT + 99 others); Fri, 20 Jul 2018 04:59:37 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:10525 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727815AbeGTI7h (ORCPT ); Fri, 20 Jul 2018 04:59:37 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Fri, 20 Jul 2018 01:12:23 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 20 Jul 2018 01:12:28 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 20 Jul 2018 01:12:28 -0700 Received: from [10.21.132.122] (172.20.13.39) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 20 Jul 2018 08:12:28 +0000 Subject: Re: [PATCH] pinctrl: tegra: fix spelling in devicetree binding document To: Marcel Ziswiler , , , CC: Marcel Ziswiler , Thierry Reding , Linus Walleij , , Rob Herring , Mark Rutland References: <20180720075235.18617-1-marcel@ziswiler.com> From: Jon Hunter Message-ID: <5e51036b-a0b0-9cb4-4698-cf830309ef8a@nvidia.com> Date: Fri, 20 Jul 2018 09:12:26 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20180720075235.18617-1-marcel@ziswiler.com> X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL106.nvidia.com (172.18.146.12) To HQMAIL101.nvidia.com (172.20.187.10) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 20/07/18 08:52, Marcel Ziswiler wrote: > From: Marcel Ziswiler > > This fixes a spelling mistake. > > Signed-off-by: Marcel Ziswiler > > --- > > Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt > index ecb5c0d25218..f4d06bb0b55a 100644 > --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt > +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt > @@ -17,7 +17,7 @@ Tegra124 adds the following optional properties for pin configuration subnodes. > The macros for options are defined in the > include/dt-binding/pinctrl/pinctrl-tegra.h. > - nvidia,enable-input: Integer. Enable the pin's input path. > - enable :TEGRA_PIN_ENABLE0 and > + enable :TEGRA_PIN_ENABLE and > disable or output only: TEGRA_PIN_DISABLE. > - nvidia,open-drain: Integer. > enable: TEGRA_PIN_ENABLE. Thanks for fixing! Can you also fix up the one in nvidia,tegra210-pinmux.txt as well? Cheers! Jon -- nvpublic