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[209.132.180.67]) by mx.google.com with ESMTP id u1-v6si1639167pgp.18.2018.07.20.05.48.04; Fri, 20 Jul 2018 05:48:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389869AbeGTNeC (ORCPT + 99 others); Fri, 20 Jul 2018 09:34:02 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:18892 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389283AbeGTNeB (ORCPT ); Fri, 20 Jul 2018 09:34:01 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Fri, 20 Jul 2018 05:45:47 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 20 Jul 2018 05:45:55 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 20 Jul 2018 05:45:55 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 20 Jul 2018 12:45:55 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 20 Jul 2018 12:45:54 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Fri, 20 Jul 2018 12:45:54 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 20 Jul 2018 05:45:54 -0700 From: Aapo Vienamo To: Ulf Hansson , Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , "Adrian Hunter" , Mikko Perttunen CC: , , , , Aapo Vienamo Subject: [PATCH 0/7] Tegra SDHCI enable 1.8 V signaling on Tegar210 and Tegra186 Date: Fri, 20 Jul 2018 15:45:39 +0300 Message-ID: <1532090746-15863-1-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Reconfigure pad voltages as part of mmc voltage switching on controllers with adjustable voltages. Allow for reconfiguration of the signaling voltage of SDMMC1 on Tegra210 P2597 and fix SDMMC4 signaling voltage regulator configuration on Tegra210 P2180. This series depends on the "Tegra PMC pinctrl pad configuration" series posted earlier. Aapo Vienamo (7): dt-bindings: Document Tegra SDHCI pinctrl bindings mmc: tegra: Reconfigure pad voltages during voltage switching arm64: dts: Add Tegra210 sdmmc pinctrl voltage states arm64: dts: Add Tegra186 sdmmc pinctrl voltage states arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1 .../bindings/mmc/nvidia,tegra20-sdhci.txt | 22 ++++++ arch/arm64/boot/dts/nvidia/tegra186.dtsi | 40 ++++++++++ arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 12 +-- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 1 - arch/arm64/boot/dts/nvidia/tegra210.dtsi | 27 +++++++ drivers/mmc/host/sdhci-tegra.c | 91 ++++++++++++++++++++-- 6 files changed, 176 insertions(+), 17 deletions(-) -- 2.7.4