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[209.132.180.67]) by mx.google.com with ESMTP id q185-v6si1804204pga.322.2018.07.20.05.48.08; Fri, 20 Jul 2018 05:48:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390431AbeGTNeN (ORCPT + 99 others); Fri, 20 Jul 2018 09:34:13 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:6228 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389740AbeGTNeM (ORCPT ); Fri, 20 Jul 2018 09:34:12 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Fri, 20 Jul 2018 05:46:13 -0700 Received: from HQMAIL105.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 20 Jul 2018 05:46:03 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 20 Jul 2018 05:46:03 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 20 Jul 2018 12:46:05 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Fri, 20 Jul 2018 12:46:05 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 20 Jul 2018 05:46:05 -0700 From: Aapo Vienamo To: Ulf Hansson , Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Adrian Hunter , Mikko Perttunen CC: , , , , Aapo Vienamo Subject: [PATCH 4/7] arm64: dts: Add Tegra186 sdmmc pinctrl voltage states Date: Fri, 20 Jul 2018 15:45:43 +0300 Message-ID: <1532090746-15863-5-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532090746-15863-1-git-send-email-avienamo@nvidia.com> References: <1532090746-15863-1-git-send-email-avienamo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add pad voltage configuration nodes for sdmmc pads with configurable voltages on Tegra186. Signed-off-by: Aapo Vienamo --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 40 ++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index b762227..7669756 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -236,6 +237,9 @@ clock-names = "sdhci"; resets = <&bpmp TEGRA186_RESET_SDMMC1>; reset-names = "sdhci"; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc1_3v3>; + pinctrl-1 = <&sdmmc1_1v8>; status = "disabled"; }; @@ -247,6 +251,9 @@ clock-names = "sdhci"; resets = <&bpmp TEGRA186_RESET_SDMMC2>; reset-names = "sdhci"; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc2_3v3>; + pinctrl-1 = <&sdmmc2_1v8>; status = "disabled"; }; @@ -258,6 +265,9 @@ clock-names = "sdhci"; resets = <&bpmp TEGRA186_RESET_SDMMC3>; reset-names = "sdhci"; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc3_3v3>; + pinctrl-1 = <&sdmmc3_1v8>; status = "disabled"; }; @@ -368,6 +378,36 @@ <0 0x0c380000 0 0x10000>, <0 0x0c390000 0 0x10000>; reg-names = "pmc", "wake", "aotag", "scratch"; + + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1-hv"; + power-source = ; + }; + + sdmmc1_1v8: sdmmc1-1v8 { + pins = "sdmmc1-hv"; + power-source = ; + }; + + sdmmc2_3v3: sdmmc2-3v3 { + pins = "sdmmc2-hv"; + power-source = ; + }; + + sdmmc2_1v8: sdmmc2-1v8 { + pins = "sdmmc2-hv"; + power-source = ; + }; + + sdmmc3_3v3: sdmmc3-3v3 { + pins = "sdmmc3-hv"; + power-source = ; + }; + + sdmmc3_1v8: sdmmc3-1v8 { + pins = "sdmmc3-hv"; + power-source = ; + }; }; ccplex@e000000 { -- 2.7.4