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a=rsa-sha256; c=relaxed/relaxed; d=Synaptics.onmicrosoft.com; s=selector1-synaptics-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ob77neFQwWzZXuBqqiBRSphmyJH0UJITR7McDJRDJPw=; b=KUl59eNYDWD1JdgyhfuO6YjCMYhsoalM873Bn+nxFIXzyrZ6zqy50H7fu5V5hVVs64iLHQ9yS9mpP3fRQI93R6F6nXD2+wep8CM/m7DwyratP1a/v7ZncalHFZ5e5L+NlSbyK6aAqjlw/166+dESIsK5EpFHTsm20W2qQRuKToE= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Jisheng.Zhang@synaptics.com; Received: from xhacker.debian (124.74.246.114) by BLUPR0301MB1569.namprd03.prod.outlook.com (2a01:111:e400:52a9::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.973.20; Tue, 24 Jul 2018 06:00:53 +0000 Date: Tue, 24 Jul 2018 13:58:37 +0800 From: Jisheng Zhang To: Rob Herring Cc: Mark Rutland , , , , Sebastian Hesselbarth Subject: Re: [PATCH 3/3] arm64: dts: synaptics: add dtsi file for Synaptics AS370 SoC Message-ID: <20180724135837.7a85fedc@xhacker.debian> In-Reply-To: <20180720152117.GB26487@rob-hp-laptop> References: <20180713171712.05f58a74@xhacker.debian> <20180713172626.5ca0e30f@xhacker.debian> <20180720152117.GB26487@rob-hp-laptop> X-Mailer: Claws Mail 3.16.0 (GTK+ 2.24.32; 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> > + interrupt-parent = <&gic>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + aliases { > > + serial0 = &uart0; > > This normally goes in the board file. All boards will use this? Yes. AFAIK, all boards will use uart0 as the serial console. But I could move it to the board file. > > > + }; > > + > > + psci { > > + compatible = "arm,psci-1.0"; > > + method = "smc"; > > + }; > > + > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + cpu0: cpu@0 { > > + compatible = "arm,cortex-a53", "arm,armv8"; > > + device_type = "cpu"; > > + reg = <0x0>; > > + enable-method = "psci"; > > + next-level-cache = <&l2>; > > + cpu-idle-states = <&CPU_SLEEP_0>; > > + }; > > + > > + cpu1: cpu@1 { > > + compatible = "arm,cortex-a53", "arm,armv8"; > > + device_type = "cpu"; > > + reg = <0x1>; > > + enable-method = "psci"; > > + next-level-cache = <&l2>; > > + cpu-idle-states = <&CPU_SLEEP_0>; > > + }; > > + > > + cpu2: cpu@2 { > > + compatible = "arm,cortex-a53", "arm,armv8"; > > + device_type = "cpu"; > > + reg = <0x2>; > > + enable-method = "psci"; > > + next-level-cache = <&l2>; > > + cpu-idle-states = <&CPU_SLEEP_0>; > > + }; > > + > > + cpu3: cpu@3 { > > + compatible = "arm,cortex-a53", "arm,armv8"; > > + device_type = "cpu"; > > + reg = <0x3>; > > + enable-method = "psci"; > > + next-level-cache = <&l2>; > > + cpu-idle-states = <&CPU_SLEEP_0>; > > + }; > > + > > + l2: cache { > > + compatible = "cache"; > > Why do you need this node? Doesn't define If the l2 node is missing, I will get below warning: [ 1.364795] Unable to detect cache hierarchy for CPU 0 reported by drivers/base/cacheinfo.c > > > + }; > > + > > + idle-states { > > + entry-method = "psci"; > > + CPU_SLEEP_0: cpu-sleep-0 { > > + compatible = "arm,idle-state"; > > + local-timer-stop; > > + arm,psci-suspend-param = <0x0010000>; > > + entry-latency-us = <75>; > > + exit-latency-us = <155>; > > + min-residency-us = <1000>; > > + }; > > + }; > > + }; > > + > > + osc: osc { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <25000000>; > > + }; > > + > > + pmu { > > + compatible = "arm,cortex-a53-pmu"; > > + interrupts = , > > + , > > + , > > + ; > > + interrupt-affinity = <&cpu0>, > > + <&cpu1>, > > + <&cpu2>, > > + <&cpu3>; > > + }; > > + > > + timer { > > + compatible = "arm,armv8-timer"; > > + interrupts = , > > + , > > + , > > + ; > > + }; > > + > > + soc@f7000000 { > > + compatible = "simple-bus"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0 0 0xf7000000 0x1000000>; > > + > > + gic: interrupt-controller@901000 { > > + compatible = "arm,gic-400"; > > + #interrupt-cells = <3>; > > + interrupt-controller; > > + reg = <0x901000 0x1000>, > > + <0x902000 0x2000>, > > + <0x904000 0x2000>, > > + <0x906000 0x2000>; > > + interrupts = ; > > + }; > > + > > + apb@e80000 { > > + compatible = "simple-bus"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0 0xe80000 0x10000>; > > + > > + uart0: uart@0c00 { > > serial@c00 will do in v2 Thanks a lot