Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp6703317imm; Tue, 24 Jul 2018 01:19:45 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeLB9LGot5zYs9jzp/0abktOwxyAdNYiWwQOkGShAIH4KnUpS9Q8p0la3iS2z51sOofpyiD X-Received: by 2002:a63:8341:: with SMTP id h62-v6mr14938953pge.298.1532420385337; Tue, 24 Jul 2018 01:19:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532420385; cv=none; d=google.com; s=arc-20160816; b=OmtsutFIZFCpdqMF8MufcWca0G/Io9u+/vmOt7End1CATjZ9Ag8kQ5OzFoRZlriNF+ AmRIuywHHKcPwhjLCJBEaoBI1NvuJYLwL4F3vjxePPs03cgWVf2J0y+m1ffEmNDwkECv otTakply07JqWNbRgocHSB6Vy2vlP/C0azkJK+owSO6eCzOyaPhrsmuyFN4IahoslGyK EaPvlv9Uy5Mz21uYjZfQP4ceNlaaAvFSDLTQk7GEo5dwsi+ZFH9HmVCyfoI7EI83Dy0H TXE8OehVcX29U5jGRBSlAvi+lnbrsMrjlQc/i0ffdec5A5TZQ3uGlkluPR7a2CZZ+GPG zvXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=941oBlQ3sH/CVcwkn8zQN8uFx4FgeQfFLlEa1WJLjVg=; b=Gm3VVdFGDDaEy2dMbP/ulesZfdodG+Xx9jCTwYmN0l81bMa/mqVSA/pmYm6lEAkMQR KEQV/KWihv48alkZMPoGSXMCL9Ka5Bj1IB0yLLjL/8fZcgi0RZx9bifoND7wiyKj/g9W es5QKWH3HQvo8DKoPLZHTY74tZDEP7QSziwOFxLMW59wj9BpGOjBLVNwUO29Lt1L4E5A ZdXU2m+toiVjiH0U9T0fxRSdZuOEySI7jOhQ92V+1sDve3h5WNj9mST7M5BAdSjxrRU1 WpFCvBx0PisVqUnbIgXKg+ytkTXF/699q0lLXu6feEsbShA7IoJV+Q+BtkEgatffZdx8 L6Lg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j21-v6si10124382pgg.303.2018.07.24.01.19.30; Tue, 24 Jul 2018 01:19:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388810AbeGXJX1 (ORCPT + 99 others); Tue, 24 Jul 2018 05:23:27 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:3361 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2388644AbeGXJWr (ORCPT ); Tue, 24 Jul 2018 05:22:47 -0400 X-UUID: 2580607beee84ca8990e88ca9a7c71bd-20180724 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 931220600; Tue, 24 Jul 2018 16:17:28 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs03n2.mediatek.inc (172.21.101.182) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 24 Jul 2018 16:17:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 24 Jul 2018 16:17:21 +0800 From: Stu Hsieh To: CK Hu , Philipp Zabel CC: David Airlie , Matthias Brugger , , , , , , Stu Hsieh Subject: [PATCH v1 07/15] drm/mediatek: add layer config to set RDMA for plane setting Date: Tue, 24 Jul 2018 16:17:07 +0800 Message-ID: <1532420235-22268-8-git-send-email-stu.hsieh@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1532420235-22268-1-git-send-email-stu.hsieh@mediatek.com> References: <1532420235-22268-1-git-send-email-stu.hsieh@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch add layer config to set RDMA for plane setting Layer config set the data address and pitch to RDMA from plane setting. Signed-off-by: Stu Hsieh --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 78a1a0057aff..4ad0715c8341 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -36,13 +36,17 @@ #define DISP_REG_RDMA_SIZE_CON_0 0x0014 #define DISP_REG_RDMA_SIZE_CON_1 0x0018 #define DISP_REG_RDMA_TARGET_LINE 0x001c +#define DISP_RDMA_MEM_SRC_PITCH 0x002c +#define DISP_RDMA_MEM_GMC_SETTING_0 0x0030 #define DISP_REG_RDMA_FIFO_CON 0x0040 #define RDMA_FIFO_UNDERFLOW_EN BIT(31) #define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) #define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size) +#define DISP_RDMA_MEM_START_ADDR 0x0f00 #define MATRIX_INT_MTX_SEL_DEFAULT 0xb00000 +#define RDMA_MEM_GMC 0x40402020 struct mtk_disp_rdma_data { unsigned int fifo_size; @@ -152,12 +156,28 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON); } +static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, + struct mtk_plane_state *state) +{ + struct mtk_plane_pending_state *pending = &state->pending; + unsigned int addr = pending->addr; + unsigned int pitch = pending->pitch & 0xffff; + + if (pending->height == 0u || pending->width == 0u) + return; + + writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR); + writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH); + writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0); +} + static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = { .config = mtk_rdma_config, .start = mtk_rdma_start, .stop = mtk_rdma_stop, .enable_vblank = mtk_rdma_enable_vblank, .disable_vblank = mtk_rdma_disable_vblank, + .layer_config = mtk_rdma_layer_config, }; static int mtk_disp_rdma_bind(struct device *dev, struct device *master, -- 2.12.5