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[209.132.180.67]) by mx.google.com with ESMTP id a64-v6si3291832pfb.224.2018.07.24.07.30.45; Tue, 24 Jul 2018 07:31:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388654AbeGXPgm (ORCPT + 99 others); Tue, 24 Jul 2018 11:36:42 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:2558 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388521AbeGXPgm (ORCPT ); Tue, 24 Jul 2018 11:36:42 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Tue, 24 Jul 2018 07:30:00 -0700 Received: from HQMAIL107.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 24 Jul 2018 07:29:52 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 24 Jul 2018 07:29:52 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 24 Jul 2018 14:29:56 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Tue, 24 Jul 2018 14:29:56 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 24 Jul 2018 07:29:56 -0700 From: Aapo Vienamo To: Ulf Hansson , Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Adrian Hunter , Mikko Perttunen CC: , , , , Aapo Vienamo Subject: [PATCH 00/10] Update the pad autocal procedure Date: Tue, 24 Jul 2018 17:29:41 +0300 Message-ID: <1532442591-5640-1-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi all, Update the tegra_sdhci_pad_autocalib() pad drive strength calibration procedure to match the ones specified in the TRMs of the more recent SoCs. This was tested on Tegra186, Tegra210, and Tegra124, although it should not break things older generations either. This series depends on the "Tegra SDHCI enable 1.8 V signaling on Tegar210 and Tegra186" series posted earlier. Aapo Vienamo (10): mmc: tegra: Poll for calibration completion mmc: tegra: Set calibration pad voltage reference mmc: tegra: Power on the calibration pad mmc: tegra: Disable card clock during pad calibration dt-bindings: Add Tegra SDHCI pad pdpu offset bindings mmc: tegra: Program pad autocal offsets from dt arm64: dts: tegra186: Add sdmmc pad auto calibration offsets arm64: dts: tegra210: Add sdmmc pad auto calibration offsets mmc: tegra: Perform pad calibration after voltage switch mmc: tegra: Enable pad calibration on Tegra210 and Tegra186 .../bindings/mmc/nvidia,tegra20-sdhci.txt | 32 +++ arch/arm64/boot/dts/nvidia/tegra186.dtsi | 20 ++ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 12 + drivers/mmc/host/sdhci-tegra.c | 242 ++++++++++++++++++++- 4 files changed, 297 insertions(+), 9 deletions(-) -- 2.7.4