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[209.132.180.67]) by mx.google.com with ESMTP id 65-v6si10766600pgi.195.2018.07.24.08.28.44; Tue, 24 Jul 2018 08:29:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388583AbeGXPlY (ORCPT + 99 others); Tue, 24 Jul 2018 11:41:24 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:16550 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388373AbeGXPlW (ORCPT ); Tue, 24 Jul 2018 11:41:22 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Tue, 24 Jul 2018 07:34:26 -0700 Received: from HQMAIL108.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 24 Jul 2018 07:34:36 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 24 Jul 2018 07:34:36 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 24 Jul 2018 14:34:36 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Tue, 24 Jul 2018 14:34:36 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 24 Jul 2018 07:34:35 -0700 From: Aapo Vienamo To: Ulf Hansson , Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Adrian Hunter , Mikko Perttunen CC: , , , , Aapo Vienamo Subject: [PATCH 04/10] mmc: tegra: Disable card clock during pad calibration Date: Tue, 24 Jul 2018 17:34:20 +0300 Message-ID: <1532442865-6391-3-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532442865-6391-1-git-send-email-avienamo@nvidia.com> References: <1532442591-5640-1-git-send-email-avienamo@nvidia.com> <1532442865-6391-1-git-send-email-avienamo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Disable the card clock during automatic pad drive strength calibration and re-enable it aftewards. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 61067b7..0de74f4 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -52,6 +52,7 @@ #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 +#define SDHCI_TEGRA_PAD_E_INPUT_OR_E_PWRD BIT(31) #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) @@ -226,11 +227,35 @@ static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) udelay(1); } +static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) +{ + bool orig_enabled; + u32 reg; + + reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + orig_enabled = reg & SDHCI_CLOCK_CARD_EN; + + if (orig_enabled == enable) + return orig_enabled; + + if (enable) + reg |= SDHCI_CLOCK_CARD_EN; + else + reg &= ~SDHCI_CLOCK_CARD_EN; + + sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); + + return orig_enabled; +} + static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) { unsigned timeout = 10; + bool card_clk_enabled; u32 reg; + card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); + tegra_sdhci_configure_cal_pad(host, true); reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); @@ -248,6 +273,8 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) tegra_sdhci_configure_cal_pad(host, false); + tegra_sdhci_configure_card_clk(host, card_clk_enabled); + if (timeout == 0) dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); } -- 2.7.4