Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp7175423imm; Tue, 24 Jul 2018 09:35:10 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdCIkRZJm+wJz7GsC27Wml8LJ3o6lqb0UAbjMWTICVXaI7qTkYPDRNe02bVH7gajBLCnoqK X-Received: by 2002:a65:498c:: with SMTP id r12-v6mr17417990pgs.112.1532450110768; Tue, 24 Jul 2018 09:35:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532450110; cv=none; d=google.com; s=arc-20160816; b=kQ71EOCn8QimLeVpfPo9O5IVCmayxEQVUCNEmtJCckff2NPGTXpEdraXpD+edBbkcq cd4f+QENlEw0yoty3hU2YYQsu2XWoZldfI9sYOyXc04QGwcboVaMXORZne+WnvC32HmU pBxAFR0WBOgjjl197zQu4Fm5YWSP8npJcOPr4rcHz3bk7T81vW5v/Mzx4e1wNE1QrHAB IuY4cSh0c+8GxEXtL9VfkRdaaQPv3wQiZWVnMmZwi3dPGzmcq4GVqbG1G/dUr0LYHPiQ sjvTFyVa8ZuOIAyTAD+19lHzuxgDtMla4ZW93oFffQfswflKcuXTex35En3Mns5P3dqj eR7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-transfer-encoding:content-disposition:mime-version :references:message-id:subject:cc:to:from:date :arc-authentication-results; bh=7OwwduiIPoW1cP2Nlsqjr07s8/ENVM7SK7KJ7jwFgg4=; b=1BlhAUqQg8AKTrA+zjWzYB1GlRL+C3YQMnWiaVIvVz0utShoyqO8Kto0lHPSVEJE/o tYHe1AWJW8Mgc9rHcWmccphNIX0v79FSwqKrV4Dg+3nppfLaSAkjvMG25PC0JjRAYzuy GAIKiowFHWrNEC4pyU4ZGOhfjbRs/FwZZF7Tn2e25j4fBu4SKIoTKDQEzuK1G6Iau/0k mzZKsOPZSydDCi/pUxoGBeJgKfePlwURcFmK7ivLCNeuqFysd0P5WAwEIcTV2rnyPBD4 LSQiJzJfJezNziVAcOuABVNnLHpxETBIWMxP/agySTXUJLQ4eptdl+vOE3NAwFWI/x4k WS/g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 79-v6si11811968pfs.40.2018.07.24.09.34.55; Tue, 24 Jul 2018 09:35:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388467AbeGXRkr (ORCPT + 99 others); Tue, 24 Jul 2018 13:40:47 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:54800 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388409AbeGXRkr (ORCPT ); Tue, 24 Jul 2018 13:40:47 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 25E9880D; Tue, 24 Jul 2018 09:33:31 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EA5FA3F5B3; Tue, 24 Jul 2018 09:33:30 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 9AB051AE3B5E; Tue, 24 Jul 2018 17:33:30 +0100 (BST) Date: Tue, 24 Jul 2018 17:33:30 +0100 From: Will Deacon To: Andy Lutomirski Cc: Rik van Riel , Peter Zijlstra , Vitaly Kuznetsov , Juergen Gross , Boris Ostrovsky , linux-arch , Catalin Marinas , linux-s390@vger.kernel.org, Benjamin Herrenschmidt , linuxppc-dev , LKML , X86 ML , Mike Galbraith , kernel-team , Ingo Molnar , Dave Hansen Subject: Re: [PATCH 4/7] x86,tlb: make lazy TLB mode lazier Message-ID: <20180724163330.GC25888@arm.com> References: <20180716190337.26133-1-riel@surriel.com> <20180716190337.26133-5-riel@surriel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Andy, Sorry, I missed the arm64 question at the end of this... On Thu, Jul 19, 2018 at 10:04:09AM -0700, Andy Lutomirski wrote: > On Thu, Jul 19, 2018 at 9:45 AM, Andy Lutomirski wrote: > > [I added PeterZ and Vitaly -- can you see any way in which this would > > break something obscure? I don't.] > > > > On Thu, Jul 19, 2018 at 7:14 AM, Rik van Riel wrote: > >> I guess we can skip both switch_ldt and load_mm_cr4 if real_prev equals > >> next? > > > > Yes, AFAICS. > > > >> > >> On to the lazy TLB mm_struct refcounting stuff :) > >> > >>> > >>> Which refcount? mm_users shouldn’t be hot, so I assume you’re talking about > >>> mm_count. My suggestion is to get rid of mm_count instead of trying to > >>> optimize it. > >> > >> > >> Do you have any suggestions on how? :) > >> > >> The TLB shootdown sent at __exit_mm time does not get rid of the > >> kernelthread->active_mm > >> pointer pointing at the mm that is exiting. > >> > > > > Ah, but that's conceptually very easy to fix. Add a #define like > > ARCH_NO_TASK_ACTIVE_MM. Then just get rid of active_mm if that > > #define is set. After some grepping, there are very few users. The > > only nontrivial ones are the ones in kernel/ and mm/mmu_context.c that > > are involved in the rather complicated dance of refcounting active_mm. > > If that field goes away, it doesn't need to be refcounted. Instead, I > > think the refcounting can get replaced with something like: > > > > /* > > * Release any arch-internal references to mm. Only called when > > mm_users is zero > > * and all tasks using mm have either been switch_mm()'d away or have had > > * enter_lazy_tlb() called. > > */ > > extern void arch_shoot_down_dead_mm(struct mm_struct *mm); > > > > which the kernel calls in __mmput() after tearing down all the page > > tables. The body can be something like: > > > > if (WARN_ON(cpumask_any_but(mm_cpumask(...), ...)) { > > /* send an IPI. Maybe just call tlb_flush_remove_tables() */ > > } > > > > (You'll also have to fix up the highly questionable users in > > arch/x86/platform/efi/efi_64.c, but that's easy.) > > > > Does all that make sense? Basically, as I understand it, the > > expensive atomic ops you're seeing are all pointless because they're > > enabling an optimization that hasn't actually worked for a long time, > > if ever. > > Hmm. Xen PV has a big hack in xen_exit_mmap(), which is called from > arch_exit_mmap(), I think. It's a heavier weight version of more or > less the same thing that arch_shoot_down_dead_mm() would be, except > that it happens before exit_mmap(). But maybe Xen actually has the > right idea. In other words, rather doing the big pagetable free in > exit_mmap() while there may still be other CPUs pointing at the page > tables, the other order might make more sense. So maybe, if > ARCH_NO_TASK_ACTIVE_MM is set, arch_exit_mmap() should be responsible > for getting rid of all secret arch references to the mm. > > Hmm. ARCH_FREE_UNUSED_MM_IMMEDIATELY might be a better name. > > I added some more arch maintainers. The idea here is that, on x86 at > least, task->active_mm and all its refcounting is pure overhead. When > a process exits, __mmput() gets called, but the core kernel has a > longstanding "optimization" in which other tasks (kernel threads and > idle tasks) may have ->active_mm pointing at this mm. This is nasty, > complicated, and hurts performance on large systems, since it requires > extra atomic operations whenever a CPU switches between real users > threads and idle/kernel threads. > > It's also almost completely worthless on x86 at least, since __mmput() > frees pagetables, and that operation *already* forces a remote TLB > flush, so we might as well zap all the active_mm references at the > same time. > > But arm64 has real HW remote flushes. Does arm64 actually benefit > from the active_mm optimization? What happens on arm64 when a process > exits? How about s390? I suspect that x390 has rather larger systems > than arm64, where the cost of the reference counting can be much > higher. IIRC, the TLB invalidation on task exit has the fullmm field set in the mmu_gather structure, so we don't actually do any TLB invalidation at all. Instead, we just don't re-allocate the ASID and invalidate the whole TLB when we run out of ASIDs (they're 16-bit on most Armv8 CPUs). Does that answer your question? Will