Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp472328imm; Wed, 25 Jul 2018 00:01:46 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdiWFBpYRIhkRJN+nem657bH0V6Ggv5RVRkDQsKktXDMw1jun/7Z05uv3bQ1OLAND3ZAE2I X-Received: by 2002:a63:338e:: with SMTP id z136-v6mr18817518pgz.171.1532502106098; Wed, 25 Jul 2018 00:01:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532502106; cv=none; d=google.com; s=arc-20160816; b=d16i6t6SFUI4o4JdVewayjkrLYO+DSnhjSsCJ9bGPF2wi16D5BXnFDPyuFEkvvwENm 40QkDtNsAfxo4udgzGk9VfSyJlrAvSXVml1HK+qZcXD8saBfiZB4srjd7vMVAOO5RugD KKGNDHFL7e/+YOHb2WVqC1sGuPXSXSUKVx0E/X6wq7Sw9v3YNPbcylmslYk9XIYUPIUs NH96zgdQ0URdkBQj2K0vgfbqV1LvrVChxU+0iuToXmiq9s0M7rJlIRHLp16+gAbIVHwR uazEkUSblGXvEJhBVh50jknSjPxhIZePCEiNfsqEL+BY+/x7iq51JGVpc4lsRDnj68sB U0bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=ZqoZN824wbidGFpnShq6cuEdJsQQchDyMvCoXxTHdRo=; b=I6ew3sHOGa5dbMLH+T9alELT62JA39ycpEZ1WPhN0we3FmPUCcqK7h2d1sX1F3QIgj fAY/KaVMxYGFnK3ZtaLQTZYe9XY48LNAXpEDuddbkWoFoFUOz9gbmBYIRPY0CW7a18Om LdKTRDy8iXksGfPhodzWPGLfavuaaG9ADGlvuaO/YI8rzkBMYReCxCgI4wX2Xccy0orr Gk1yCK6tLjiH9iY+iNSBgIh8cdJJUZB/bxivgTOdyy11s8Nl4IUGtH1Ha0V4keRy9hc4 9AFNgT6H/lU42yKRPdnxWZczV0SOqAVrOGuHn3unTRjWyqwfkGn7rU09dFvNWFBV5tnV OcRg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r69-v6si13482772pfl.260.2018.07.25.00.01.31; Wed, 25 Jul 2018 00:01:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728809AbeGYIJi (ORCPT + 99 others); Wed, 25 Jul 2018 04:09:38 -0400 Received: from mo4-p04-ob.smtp.rzone.de ([85.215.255.123]:18513 "EHLO mo4-p04-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728718AbeGYIJh (ORCPT ); Wed, 25 Jul 2018 04:09:37 -0400 X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMhflhwDubTJ9o12DNO4Ij0pB1ZSLA74=" X-RZG-CLASS-ID: mo00 Received: from iMac.fritz.box by smtp.strato.de (RZmta 43.13 DYNA|AUTH) with ESMTPSA id 6047f4u6P6xCd5j (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (curve secp521r1 with 521 ECDH bits, eq. 15360 bits RSA)) (Client did not present a certificate); Wed, 25 Jul 2018 08:59:12 +0200 (CEST) From: "H. Nikolaus Schaller" To: Marek Belisko , =?UTF-8?q?Beno=C3=AEt=20Cousson?= , Tony Lindgren , Rob Herring , Mark Rutland Cc: linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, letux-kernel@openphoenux.org, "H. Nikolaus Schaller" Subject: [PATCH 20/32] ARM: dts: omap3-gta04: add devconf0 setup for mcbsp1 clock pins Date: Wed, 25 Jul 2018 08:58:52 +0200 Message-Id: <5dbe024d9465eab668ba9aac3732ded225859e6f.1532501910.git.hns@goldelico.com> X-Mailer: git-send-email 2.12.2 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org McBSP1 needs sepcial "pinctrl" for the clocks. Signed-off-by: H. Nikolaus Schaller --- arch/arm/boot/dts/omap3-gta04.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 935a2a707737..f6abdef556c1 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -187,6 +187,24 @@ reset-gpios = <&tca6507 0 GPIO_ACTIVE_LOW>; /* W2CBW003 reset through tca6507 */ }; + /* devconf0 setup for mcbsp1 clock pins */ + pinmux_mcbsp1@48002274 { + compatible = "pinctrl-single"; + reg = <0x48002274 4>; /* CONTROL_DEVCONF0 */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,bit-per-mux; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x7>; /* MCBSP1 CLK pinmux */ + #pinctrl-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp1_devconf0_pins>; + mcbsp1_devconf0_pins: pinmux_mcbsp1_devconf0_pins { + /* offset bits mask */ + pinctrl-single,bits = <0x00 0x08 0x1c>; /* set MCBSP1_CLKR */ + }; + }; + /* devconf1 setup for tvout pins */ pinmux_tv_out@480022d8 { compatible = "pinctrl-single"; -- 2.12.2