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Subject: Re: [PATCH 1/3] mtd: spi-nor: add Global Block Unlock support
To:     Tudor Ambarus <tudor.ambarus@microchip.com>,
        <marek.vasut@gmail.com>, <dwmw2@infradead.org>,
        <computersforpeace@gmail.com>, <boris.brezillon@bootlin.com>,
        <richard@nod.at>
CC:     <linux-mtd@lists.infradead.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>, <anuragku@xilinx.com>,
        <nicolas.ferre@microchip.com>
References: <20180717162831.17947-1-tudor.ambarus@microchip.com>
From:   Cyrille Pitchen <cyrille.pitchen@microchip.com>
Message-ID: <8e0ff8be-34d1-7de9-6120-a067540a75d2@microchip.com>
Date:   Wed, 25 Jul 2018 14:26:36 +0200
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Hi Tudor,

Le 17/07/2018 à 18:28, Tudor Ambarus a écrit :
> We can't determine this purely by manufacturer type and it's not
> autodetectable by anything like SFDP, so make a new flag for it:
> UNLOCK_GLOBAL_BLOCK.
> 
> Note that the Global Block Unlock command has different names
> depending on the manufacturer, but always the same command value:
> 0x98. Macronix's MX25U12835F names it Gang Block Unlock,
> Winbound's W25Q128FV names it Global Block Unlock and
> Microchip's SST26VF064B names it Global Block Protection Unlock.
> 
> Based on initial work done by Anurag Kumar Vulisha:
> https://patchwork.kernel.org/patch/7611271/
> 
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>

Reviewed-by: Cyrille Pitchen <cyrille.pitchen@microchip.com>

Best regards,

Cyrille
> ---
>  drivers/mtd/spi-nor/spi-nor.c | 21 +++++++++++++++++++++
>  include/linux/mtd/spi-nor.h   |  1 +
>  2 files changed, 22 insertions(+)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index d9c368c..6648251 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -89,6 +89,7 @@ struct flash_info {
>  #define NO_CHIP_ERASE		BIT(12) /* Chip does not support chip erase */
>  #define SPI_NOR_SKIP_SFDP	BIT(13)	/* Skip parsing of SFDP tables */
>  #define USE_CLSR		BIT(14)	/* use CLSR command */
> +#define UNLOCK_GLOBAL_BLOCK	BIT(15)	/* Unlock global block protection */
>  
>  	int	(*quad_enable)(struct spi_nor *nor);
>  };
> @@ -2730,6 +2731,17 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
>  	return 0;
>  }
>  
> +static int spi_nor_unlock_global_block_protection(struct spi_nor *nor)
> +{
> +	int ret;
> +
> +	write_enable(nor);
> +	ret = nor->write_reg(nor, SPINOR_OP_GBULK, NULL, 0);
> +	if (ret < 0)
> +		return ret;
> +	return spi_nor_wait_till_ready(nor);
> +}
> +
>  static int spi_nor_init(struct spi_nor *nor)
>  {
>  	int err;
> @@ -2747,6 +2759,15 @@ static int spi_nor_init(struct spi_nor *nor)
>  		spi_nor_wait_till_ready(nor);
>  	}
>  
> +	if (nor->info->flags & UNLOCK_GLOBAL_BLOCK) {
> +		err = spi_nor_unlock_global_block_protection(nor);
> +		if (err) {
> +			dev_err(nor->dev,
> +				"Cannot unlock the global block protection\n");
> +			return err;
> +		}
> +	}
> +
>  	if (nor->quad_enable) {
>  		err = nor->quad_enable(nor);
>  		if (err) {
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index e60da0d..e8dd11d 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -64,6 +64,7 @@
>  #define SPINOR_OP_CLFSR		0x50	/* Clear flag status register */
>  #define SPINOR_OP_RDEAR		0xc8	/* Read Extended Address Register */
>  #define SPINOR_OP_WREAR		0xc5	/* Write Extended Address Register */
> +#define SPINOR_OP_GBULK		0x98	/* Global Block Unlock Protection */
>  
>  /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
>  #define SPINOR_OP_READ_4B	0x13	/* Read data bytes (low frequency) */
>