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[209.132.180.67]) by mx.google.com with ESMTP id w9-v6si14761533pfg.234.2018.07.25.09.07.30; Wed, 25 Jul 2018 09:07:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729344AbeGYRSa (ORCPT + 99 others); Wed, 25 Jul 2018 13:18:30 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:41508 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728600AbeGYRSa (ORCPT ); Wed, 25 Jul 2018 13:18:30 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3EB1C80D; Wed, 25 Jul 2018 09:06:11 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0EED13F575; Wed, 25 Jul 2018 09:06:11 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 0E19F1AE1110; Wed, 25 Jul 2018 17:06:10 +0100 (BST) Date: Wed, 25 Jul 2018 17:06:10 +0100 From: Will Deacon To: Johannes Weiner Cc: Arnd Bergmann , Peter Zijlstra , Suren Baghdasaryan , Mike Galbraith , Linux Kernel Mailing List , kernel-team@fb.com, Linux-MM , Vinayak Menon , Ingo Molnar , Shakeel Butt , Catalin Marinas , Tejun Heo , cgroups@vger.kernel.org, Andrew Morton , Linus Torvalds , Christopher Lameter , Linux ARM Subject: Re: [PATCH 02/10] mm: workingset: tell cache transitions from workingset thrashing Message-ID: <20180725160610.GD6866@arm.com> References: <20180712172942.10094-1-hannes@cmpxchg.org> <20180712172942.10094-3-hannes@cmpxchg.org> <20180723152323.GA3699@cmpxchg.org> <20180723162735.GA5980@cmpxchg.org> <20180724150448.GA25412@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180724150448.GA25412@arm.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jul 24, 2018 at 04:04:48PM +0100, Will Deacon wrote: > On Mon, Jul 23, 2018 at 12:27:35PM -0400, Johannes Weiner wrote: > > On Mon, Jul 23, 2018 at 05:35:35PM +0200, Arnd Bergmann wrote: > > > On Mon, Jul 23, 2018 at 5:23 PM, Johannes Weiner wrote: > > > > diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c > > > > index 1b18b4722420..72c9b6778b0a 100644 > > > > --- a/arch/arm64/mm/init.c > > > > +++ b/arch/arm64/mm/init.c > > > > @@ -611,11 +611,13 @@ void __init mem_init(void) > > > > BUILD_BUG_ON(TASK_SIZE_32 > TASK_SIZE_64); > > > > #endif > > > > > > > > +#ifndef CONFIG_SPARSEMEM_VMEMMAP > > > > /* > > > > > > I tested it on two broken configurations, and found that you have > > > a typo here, it should be 'ifdef', not 'ifndef'. With that change, it > > > seems to build fine. > > > > > > Tested-by: Arnd Bergmann > > > > Thanks for testing it, I don't have a cross-compile toolchain set up. > > > > --- > > Thanks Arnd, Johannes. I can pick this up for -rc7 via the arm64 tree, > unless it's already queued elsewhere? I've pushed this to the arm64 for-next/fixes branch heading for -rc7. Will