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[209.85.167.48]) by smtp.gmail.com with ESMTPSA id f3-v6sm2345861lfc.30.2018.07.25.13.26.55 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 25 Jul 2018 13:26:55 -0700 (PDT) Received: by mail-lf1-f48.google.com with SMTP id f135-v6so4608891lfg.10 for ; Wed, 25 Jul 2018 13:26:55 -0700 (PDT) X-Received: by 2002:a19:f70d:: with SMTP id z13-v6mr13410732lfe.33.1532550415054; Wed, 25 Jul 2018 13:26:55 -0700 (PDT) MIME-Version: 1.0 References: <20180619083647.10116-1-cang@codeaurora.org> <20180619083647.10116-2-cang@codeaurora.org> In-Reply-To: From: Evan Green Date: Wed, 25 Jul 2018 13:26:18 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v7 1/4] phy: Update PHY power control sequence To: vivek.gautam@codeaurora.org Cc: cang@codeaurora.org, subhashj@codeaurora.org, asutoshd@codeaurora.org, Manu Gautam , kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jul 2, 2018 at 10:00 AM Vivek Gautam wrote: > > On Tue, Jun 19, 2018 at 2:06 PM, Can Guo wrote: > > All PHYs should be powered on before register configuration starts. And > > only PCIe PHYs need an extra power control before deasserts reset state. > > > > Signed-off-by: Can Guo > > --- > > drivers/phy/qualcomm/phy-qcom-qmp.c | 19 ++++++++++++------- > > 1 file changed, 12 insertions(+), 7 deletions(-) > > Reviewed-by: Evan Green