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[46.139.12.213]) by smtp.gmail.com with ESMTPSA id j9-v6sm4671917wrv.5.2018.07.26.12.06.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 26 Jul 2018 12:06:35 -0700 (PDT) Date: Thu, 26 Jul 2018 21:06:33 +0200 From: Ingo Molnar To: Pavel Machek Cc: Henrique de Moraes Holschuh , Jan Beulich , mingo@elte.hu, rdunlap@infradead.org, tglx@linutronix.de, hpa@zytor.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH] x86-64: use 32-bit XOR to zero registers Message-ID: <20180726190633.GA25081@gmail.com> References: <5B30C32902000078001CD6D5@prv1-mh.provo.novell.com> <5B31DDFF02000078001CDC03@prv1-mh.provo.novell.com> <20180626113822.ch3erlyud5wsxvvg@khazad-dum.debian.net> <20180726091916.GA23471@amd> <20180726114537.GA12408@gmail.com> <20180726181750.GA4404@amd> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180726181750.GA4404@amd> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Pavel Machek wrote: > On Thu 2018-07-26 13:45:37, Ingo Molnar wrote: > > > > * Pavel Machek wrote: > > > > > On Tue 2018-06-26 08:38:22, Henrique de Moraes Holschuh wrote: > > > > On Tue, 26 Jun 2018, Jan Beulich wrote: > > > > > >>> On 25.06.18 at 18:33, wrote: > > > > > > On 06/25/2018 03:25 AM, Jan Beulich wrote: > > > > > >> Some Intel CPUs don't recognize 64-bit XORs as zeroing idioms - use > > > > > >> 32-bit ones instead. > > > > > > > > > > > > Hmph. Is that considered a bug (errata)? > > > > > > > > > > No. > > > > > > > > > > > URL/references? > > > > > > > > > > Intel's Optimization Reference Manual says so (in rev 040 this is in section > > > > > 16.2.2.5 "Zeroing Idioms" as a subsection of the Goldmont/Silvermont > > > > > descriptions). > > > > > > > > > > > Are these changes really only zeroing the lower 32 bits of the register? > > > > > > and that's all that the code cares about? > > > > > > > > > > No - like all operations targeting a 32-bit register, the result is zero > > > > > extended to the entire 64-bit destination register. > > > > > > > > Missing information that would have been helpful in the commit message: > > > > > > > > When the processor can recognize something as a zeroing idiom, it > > > > optimizes that operation on the front-end. Only 32-bit XOR r,r is > > > > documented as a zeroing idiom according to the Intel optimization > > > > manual. While a few Intel processors recognize the 64-bit version of > > > > XOR r,r as a zeroing idiom, many won't. > > > > > > > > Note that the 32-bit operation extends to the high part of the 64-bit > > > > register, so it will zero the entire 64-bit register. The 32-bit > > > > instruction is also one byte shorter. > > > > > > Actually, I believe that should be comment in code. > > > > Agreed - mind sending a patch that adds it? > > Ok. Would /* write to low 32 bits clears high 32 bits, too */ be > reasonable comment? So I'd suggest putting the above description somewhere strategic - such as the top of entry_64.S, or calling.h, or so? Thanks, Ingo