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[209.132.180.67]) by mx.google.com with ESMTP id c18-v6si3374067pgh.530.2018.07.27.01.07.35; Fri, 27 Jul 2018 01:07:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730205AbeG0J0s (ORCPT + 99 others); Fri, 27 Jul 2018 05:26:48 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:16333 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729445AbeG0J0s (ORCPT ); Fri, 27 Jul 2018 05:26:48 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Fri, 27 Jul 2018 01:05:54 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 27 Jul 2018 01:06:05 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 27 Jul 2018 01:06:05 -0700 Received: from dhcp-10-21-25-168 (10.21.25.201) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 27 Jul 2018 08:06:01 +0000 Date: Fri, 27 Jul 2018 11:05:55 +0300 From: Aapo Vienamo To: Stefan Agner CC: Ulf Hansson , Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , "Adrian Hunter" , Mikko Perttunen , , , , , Subject: Re: [PATCH v2 02/10] dt-bindings: mmc: tegra: Add nvidia,only-1-8-v property Message-ID: <20180727110555.1b7ad97d@dhcp-10-21-25-168> In-Reply-To: <484a31bdaad6d76b4fbb7d6fa80cbb8d@agner.ch> References: <1532607560-11253-1-git-send-email-avienamo@nvidia.com> <1532607560-11253-3-git-send-email-avienamo@nvidia.com> <484a31bdaad6d76b4fbb7d6fa80cbb8d@agner.ch> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.21.25.201] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To HQMAIL101.nvidia.com (172.20.187.10) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 26 Jul 2018 15:05:55 +0200 Stefan Agner wrote: > On 26.07.2018 14:19, Aapo Vienamo wrote: > > Add a property to mark controllers which operate at a 1.8 V fixed I/O > > voltage. > > > > This feature of the hardware needs to be signaled this way because it > > cannot be probed at runtime or reliably derived from other properties. > > Is this really needed? Can we not use vqmmc to determine which voltage > the controller runs on? > > There is already some precedence in the SDHCI core to determine which > voltage levels are supported: > https://lkml.org/lkml/2018/7/5/342 This property is introduced to solve a slightly different issue. The thing is that supplying a fixed voltage SDHCI controller from a variable regulator is still a valid configuration. Which means that testing the capabilities of the regulator doesn't actually describe the SDHCI controller itself. In practice this property is used to communicate whether pad reconfiguration and voltage switching needs to be performed or not. This cannot be determined from the absence or presence of the pinctrl properties either because they naturally won't be there on older dtbs. The logic behind this goes like this: if this property is present, there's no need to perform pad or regulator reconfiguration and UHS modes can be enabled. If this property is missing then valid pinctrl and regulator properties are required to enable UHS signaling. This is implemented in tegra_sdhci_is_uhs_valid() in "[PATCH v2 03/10] mmc: tegra: Reconfigure pad voltages during voltage switching" -Aapo