Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp776766imm; Fri, 27 Jul 2018 06:02:41 -0700 (PDT) X-Google-Smtp-Source: AAOMgpegiJ2oaXKGrxlkdx5l4dzEAwBo7KYvZMr/G3LpJqWMq7m3Nio8CYxMUJ4CRlINZnk/LXpS X-Received: by 2002:a63:7a43:: with SMTP id j3-v6mr5988749pgn.363.1532696561202; Fri, 27 Jul 2018 06:02:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532696561; cv=none; d=google.com; s=arc-20160816; b=0EUvJ1Sgv+96NdZR4CXIa0zNQFz04dJkQgpFkwE4NNiq9zdkNlvp3sJBKBj1A4yy/9 vxHMkBQocJ2sQ9uZv4sjnEo1sysGIOzlcTVC+m172odM5KU44sbaABsSQ7SR5Xl4+NVC 8qUQqjbxZxSa9H+CUaGDwjugGWQCfNR1Ax+phP8SATXLNQli8TbxGvsz8wqFwhbB/LpB z6ySLnI0NahSBT3GJg416NGVmgShIPj/pksbewXmribgaQENjk/B54KMoXoCRTdgad76 Ldts3R5/U1IE3p5VaI0Ih2kQ6GAb/FVmFHTWi9VMogBEtPD4Ub/ZCyvdndQ0GOA8bMuz GBJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=982Z9dwqMcf8YTu/6wVheSK74MyNoZi2JTc+/8Zuovo=; b=nF88WboEDELS1abPhldM+bzSN89kK7cOeUul8hHyRKwEnh+nFXnd5jSmlYiTiPHBby mb5E3+hvIl95W+nMNuifzIvAoRUi9kB0SjMkPgDLwuhYnWOz8PljUubK6/sd04s5YIAa hYK9oy6EJEtUiJUs99jdm0jSg4JC7eQjALiRy9eUGGgmYhZOgUn+fFXQh0n4H8zznGK/ pJO1hPRSjHVcI/tEjP5TzLt7EA/J32G/zemeXgsJybcQhtJiNkgws5d/GmFQk/XuXOVD FB9Mh8g3+SnrydQ4RtoPlhBXw8zSMN5AhBY4LDwijbVZEButaqXdCgofEY1PzT/OWXPX u6pg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=codethink.co.uk Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h65-v6si4417665pfb.70.2018.07.27.06.02.26; Fri, 27 Jul 2018 06:02:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=codethink.co.uk Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732165AbeG0OV3 (ORCPT + 99 others); Fri, 27 Jul 2018 10:21:29 -0400 Received: from imap1.codethink.co.uk ([176.9.8.82]:57516 "EHLO imap1.codethink.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731100AbeG0OV3 (ORCPT ); Fri, 27 Jul 2018 10:21:29 -0400 Received: from [148.252.241.226] (helo=ct-lt-1121.office.codethink.co.uk) by imap1.codethink.co.uk with esmtpsa (Exim 4.84_2 #1 (Debian)) id 1fj2LG-0008VU-V5; Fri, 27 Jul 2018 13:59:35 +0100 From: Jorge Sanjuan To: lgirdwood@gmail.com, broonie@kernel.org Cc: jonathanh@nvidia.com, thierry.reding@gmail.com, alsa-devel@alsa-project.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kernel@lists.codethink.co.uk Subject: [PATCH 1/4] ASoC: tegra: i2s: Fix typo/broken macro Date: Fri, 27 Jul 2018 13:59:28 +0100 Message-Id: <20180727125931.9794-2-jorge.sanjuan@codethink.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180727125931.9794-1-jorge.sanjuan@codethink.co.uk> References: <20180727125931.9794-1-jorge.sanjuan@codethink.co.uk> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Edward Cragg Fix typo in macro TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK. Signed-off-by: Edward Cragg Signed-off-by: Jorge Sanjuan --- sound/soc/tegra/tegra30_i2s.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/tegra/tegra30_i2s.h b/sound/soc/tegra/tegra30_i2s.h index 774fc6ad2026..2e561e946de2 100644 --- a/sound/soc/tegra/tegra30_i2s.h +++ b/sound/soc/tegra/tegra30_i2s.h @@ -173,7 +173,7 @@ /* Number of slots in frame, minus 1 */ #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT 16 #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US 7 -#define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK (TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOT_MASK_US << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOT_SHIFT) +#define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK (TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT) /* TDM mode slot enable bitmask */ #define TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT 8 -- 2.11.0