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Date:   Sun, 29 Jul 2018 12:35:10 -0700 (PDT)
Message-Id: <20180729.123510.1847228041867717113.davem@davemloft.net>
To:     Eugeniy.Paltsev@synopsys.com
Cc:     netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-snps-arc@lists.infradead.org, Jose.Abreu@synopsys.com,
        alexandre.torgue@st.com, peppe.cavallaro@st.com
Subject: Re: [PATCH] NET: stmmac: align DMA stuff to largest cache line
 length
From:   David Miller <davem@davemloft.net>
In-Reply-To: <20180726120537.4664-1-Eugeniy.Paltsev@synopsys.com>
References: <20180726120537.4664-1-Eugeniy.Paltsev@synopsys.com>
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From: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Date: Thu, 26 Jul 2018 15:05:37 +0300

> As for today STMMAC_ALIGN macro (which is used to align DMA stuff)
> relies on L1 line length (L1_CACHE_BYTES).
> This isn't correct in case of system with several cache levels
> which might have L1 cache line length smaller than L2 line. This
> can lead to sharing one cache line between DMA buffer and other
> data, so we can lose this data while invalidate DMA buffer before
> DMA transaction.
> 
> Fix that by using SMP_CACHE_BYTES instead of L1_CACHE_BYTES for
> aligning.
> 
> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>

This is definitely an improvement, so applied and queued up for
-stable.

There is also dma_get_cache_alignment(), so maybe we can eventually
use that here instead.