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[209.132.180.67]) by mx.google.com with ESMTP id g10-v6si9648399pge.694.2018.07.29.20.12.52; Sun, 29 Jul 2018 20:13:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linux.com header.s=cjonuzaf4apohm6q2sqksleozwz3sz4m header.b=C9m7rjGa; dkim=pass header.i=@amazonses.com header.s=7v7vs6w47njt4pimodk5mmttbegzsi6n header.b=Lj+NZilS; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726322AbeG3Eou (ORCPT + 99 others); Mon, 30 Jul 2018 00:44:50 -0400 Received: from a27-29.smtp-out.us-west-2.amazonses.com ([54.240.27.29]:53896 "EHLO a27-29.smtp-out.us-west-2.amazonses.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725811AbeG3Eou (ORCPT ); Mon, 30 Jul 2018 00:44:50 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/simple; s=cjonuzaf4apohm6q2sqksleozwz3sz4m; d=linux.com; t=1532920319; h=MIME-Version:In-Reply-To:References:From:Date:Message-ID:Subject:To:Cc:Content-Type; bh=2PwFsEdYNVBQpeO3I09Xc1E+3KeKa5cwiwV9D1ds7AQ=; b=C9m7rjGaQYA1PdRk+Xa1hDke7J7BQfISHfZ0VWy2S5yZn6jhaByq5tXodIfJRke/ s7stqZgoCEQq/MUIdwsLKZeVAhWFs0xWyFyt1vlc1ZoQusNcoMt7PKrkcSdFmsnFxxG yeUQao9JU+P2rMft1WHZeyFGkMutbTfLeByoOlgk= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/simple; s=7v7vs6w47njt4pimodk5mmttbegzsi6n; d=amazonses.com; t=1532920319; h=MIME-Version:In-Reply-To:References:From:Date:Message-ID:Subject:To:Cc:Content-Type:Feedback-ID; bh=2PwFsEdYNVBQpeO3I09Xc1E+3KeKa5cwiwV9D1ds7AQ=; b=Lj+NZilSiUtTbF4L4Qp0J1+T0Khi7YNXTJBW+GTcLD1+29J4vYT1yjUnizOeq/P4 avg84POWTwB6mpUBaN9/FiYmq4LIkum+DG9bStNpU8AOn+9BbFh0UrNhUX4MTOy5vIb /hety6DtAfTaYfuCHtQ4ZCHq5qjCv0LCh1K8m+pY= X-Gm-Message-State: AOUpUlFnESB4fD3Chcn9IwOctkw5hR+xPy3HbTZr436bQNLddt7MpqIO ZIm65YT7qM34/GKU9ZrOkgmRSuQjltpKhgpoZfY= X-Received: by 2002:a0d:c4c2:: with SMTP id g185-v6mr7780001ywd.49.1532920315699; Sun, 29 Jul 2018 20:11:55 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <20180730105954.6c365a7b@xhacker.debian> References: <20180730104228.28b58bd0@xhacker.debian> <20180730104636.1a3e6c81@xhacker.debian> <01010164e91d7bda-aa616cbf-7bb2-4fe4-85e5-a18e16433fde-000000@us-west-2.amazonses.com> <20180730105954.6c365a7b@xhacker.debian> From: Matthew Leon Date: Mon, 30 Jul 2018 03:11:59 +0000 X-Gmail-Original-Message-ID: Message-ID: <01010164e92bcc18-d4fd119e-62e5-4aba-a6e3-9d5787f31a1b-000000@us-west-2.amazonses.com> Subject: Re: [PATCH mmc-next v3 3/3] mmc: sdhci-of-dwcmshc: solve 128MB DMA boundary limitation To: Jisheng Zhang Cc: Adrian Hunter , Ulf Hansson , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: multipart/alternative; boundary="000000000000e2ee1c05722ed231" X-SES-Outgoing: 2018.07.30-54.240.27.29 Feedback-ID: 1.us-west-2.3ULHQnc20aILdVzjlbQ8UqO1WRWzA1U01b2uFAcT62w=:AmazonSES Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --000000000000e2ee1c05722ed231 Content-Type: text/plain; charset="UTF-8" >> Hey Jisheng, >Hi, >> >In LKML, we'd better not top post. Noted. My apologies. >> Shouldn't we be splitting until all DMA blocks are less than 128M boundary? >> I am a noob, but I think we should be prepared for boundaries that when >> split in two, will still be greater than 128M. Feel free to disagree but >> please explain why I may be wrong. Thank-you. >the limitation is "DMA addr can't span 128MB boundary" rather than "must be >less than 128MB", they are different. >And the max transfer size of one DMA desc is 64KB. >thanks I have misspoken. What if the DMA transfer size is 1024M? If we split in two, then we have 2 transfers, each of which span 512M. So wouldn't we need to split again to have 4 transfers, each of which span 128M? Sincerely, Matthew Leon On Sun, Jul 29, 2018 at 10:59 PM, Jisheng Zhang wrote: > On Mon, 30 Jul 2018 02:56:20 +0000 Matthew Leon > wrote: > > > Hey Jisheng, > > Hi, > > > > > In LKML, we'd better not top post. > > > Shouldn't we be splitting until all DMA blocks are less than 128M > boundary? > > I am a noob, but I think we should be prepared for boundaries that when > > split in two, will still be greater than 128M. Feel free to disagree but > > please explain why I may be wrong. Thank-you. > > the limitation is "DMA addr can't span 128MB boundary" rather than "must be > less than 128MB", they are different. > > And the max transfer size of one DMA desc is 64KB. > > thanks > > > > > Sincerely, > > Matthew Leon > > > > On Sun, Jul 29, 2018 at 10:46 PM, Jisheng Zhang < > Jisheng.Zhang@synaptics.com > > > wrote: > > > > > When using DMA, if the DMA addr spans 128MB boundary, we have to split > > > the DMA transfer into two so that each one doesn't exceed the boundary. > > > > > > Signed-off-by: Jisheng Zhang > > > --- > > > drivers/mmc/host/sdhci-of-dwcmshc.c | 43 > +++++++++++++++++++++++++++++ > > > 1 file changed, 43 insertions(+) > > > > > > diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c > > > b/drivers/mmc/host/sdhci-of-dwcmshc.c > > > index 1b7cd144fb01..e890fc8f5284 100644 > > > --- a/drivers/mmc/host/sdhci-of-dwcmshc.c > > > +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c > > > @@ -8,21 +8,52 @@ > > > */ > > > > > > #include > > > +#include > > > #include > > > #include > > > +#include > > > > > > #include "sdhci-pltfm.h" > > > > > > +#define BOUNDARY_OK(addr, len) \ > > > + ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1))) > > > + > > > struct dwcmshc_priv { > > > struct clk *bus_clk; > > > }; > > > > > > +/* > > > + * if DMA addr spans 128MB boundary, we split the DMA transfer into > two > > > + * so that the DMA transfer doesn't exceed the boundary. > > > + */ > > > +static unsigned int dwcmshc_adma_write_desc(struct sdhci_host *host, > > > + void *desc, dma_addr_t > addr, > > > + int len, unsigned int cmd) > > > +{ > > > + int tmplen, offset; > > > + > > > + if (likely(!len || BOUNDARY_OK(addr, len))) > > > + return _sdhci_adma_write_desc(host, desc, addr, len, > cmd); > > > + > > > + offset = addr & (SZ_128M - 1); > > > + tmplen = SZ_128M - offset; > > > + _sdhci_adma_write_desc(host, desc, addr, tmplen, cmd); > > > + > > > + addr += tmplen; > > > + len -= tmplen; > > > + desc += host->desc_sz; > > > + _sdhci_adma_write_desc(host, desc, addr, len, cmd); > > > + > > > + return host->desc_sz * 2; > > > +} > > > + > > > static const struct sdhci_ops sdhci_dwcmshc_ops = { > > > .set_clock = sdhci_set_clock, > > > .set_bus_width = sdhci_set_bus_width, > > > .set_uhs_signaling = sdhci_set_uhs_signaling, > > > .get_max_clock = sdhci_pltfm_clk_get_max_clock, > > > .reset = sdhci_reset, > > > + .adma_write_desc = dwcmshc_adma_write_desc, > > > }; > > > > > > static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = { > > > @@ -36,12 +67,24 @@ static int dwcmshc_probe(struct platform_device > *pdev) > > > struct sdhci_host *host; > > > struct dwcmshc_priv *priv; > > > int err; > > > + u32 extra; > > > > > > host = sdhci_pltfm_init(pdev, &sdhci_dwcmshc_pdata, > > > sizeof(struct dwcmshc_priv)); > > > if (IS_ERR(host)) > > > return PTR_ERR(host); > > > > > > + /* > > > + * The DMA descriptor table number is calculated as the maximum > > > + * number of segments times 2, to allow for an alignment > > > + * descriptor for each segment, plus 1 for a nop end > descriptor, > > > + * plus extra number for cross 128M boundary handling. > > > + */ > > > + extra = DIV_ROUND_UP(totalram_pages, SZ_128M / PAGE_SIZE); > > > + if (extra > SDHCI_MAX_SEGS) > > > + extra = SDHCI_MAX_SEGS; > > > + host->adma_table_num = SDHCI_MAX_SEGS * 2 + 1 + extra; > > > + > > > pltfm_host = sdhci_priv(host); > > > priv = sdhci_pltfm_priv(pltfm_host); > > > > > > -- > > > 2.18.0 > > > > > > > > --000000000000e2ee1c05722ed231 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
>> Hey Jisheng,

>Hi,

>>

>In LKML, we'd better not top post.

<= /span>
Noted. My apologies.

=
>> Shouldn't we be splitting until all DMA blocks are less than 1= 28M boundary?
>> I am a noob, but I think we should be prepared for boundaries that= when
>> split in two, will still be greater than 128M. Feel free to disagr= ee but
>> please explain why I may be wrong. Thank-you.

>the limitation is "DMA addr can't span 128MB boundary&q= uot; rather than "must be
>less than 128MB", they are different.

>And the max transfer size of one DMA desc is 64KB.

>thanks

I have misspoken. What=20 if the DMA transfer size is 1024M? If we split in two, then we have 2=20 transfers, each of which span 512M. So wouldn't we need to split again= =20 to have 4 transfers, each of which span 128M?

Sinc= erely,
Matthew Leon


On Sun,= Jul 29, 2018 at 10:59 PM, Jisheng Zhang <Jisheng.Zhang@synaptic= s.com> wrote:
On Mon, 30 Ju= l 2018 02:56:20 +0000 Matthew Leon <matthewleon@linux.com> wrote:

> Hey Jisheng,

Hi,

>

In LKML, we'd better not top post.

> Shouldn't we be splitting until all DMA blocks are less than 128M = boundary?
> I am a noob, but I think we should be prepared for boundaries that whe= n
> split in two, will still be greater than 128M. Feel free to disagree b= ut
> please explain why I may be wrong. Thank-you.

the limitation is "DMA addr can't span 128MB boundary"= rather than "must be
less than 128MB", they are different.

And the max transfer size of one DMA desc is 64KB.

thanks

>
> Sincerely,
> Matthew Leon
>
> On Sun, Jul 29, 2018 at 10:46 PM, Jisheng Zhang <Jisheng.Zhang@synaptics.com
> > wrote:=C2=A0
>
> > When using DMA, if the DMA addr spans 128MB boundary, we have to = split
> > the DMA transfer into two so that each one doesn't exceed the= boundary.
> >
> > Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
> > ---
> >=C2=A0 drivers/mmc/host/sdhci-of-dwcmshc.c | 43 +++++++++++++= ++++++++++++++++
> >=C2=A0 1 file changed, 43 insertions(+)
> >
> > diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c
> > b/drivers/mmc/host/sdhci-of-dwcmshc.c
> > index 1b7cd144fb01..e890fc8f5284 100644
> > --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> > +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> > @@ -8,21 +8,52 @@
> >=C2=A0 =C2=A0*/
> >
> >=C2=A0 #include <linux/clk.h>
> > +#include <linux/mm.h>
> >=C2=A0 #include <linux/module.h>
> >=C2=A0 #include <linux/of.h>
> > +#include <linux/sizes.h>
> >
> >=C2=A0 #include "sdhci-pltfm.h"
> >
> > +#define BOUNDARY_OK(addr, len) \
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0((addr | (SZ_128M - 1)) =3D=3D ((addr= + len - 1) | (SZ_128M - 1)))
> > +
> >=C2=A0 struct dwcmshc_priv {
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0struct clk=C2=A0 =C2=A0 =C2=A0 *= bus_clk;
> >=C2=A0 };
> >
> > +/*
> > + * if DMA addr spans 128MB boundary, we split the DMA transfer i= nto two
> > + * so that the DMA transfer doesn't exceed the boundary.
> > + */
> > +static unsigned int dwcmshc_adma_write_desc(struct sdhci_host *h= ost,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0void *desc, dma_addr_t addr,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0int len, unsigned int cmd)
> > +{
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0int tmplen, offset;
> > +
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0if (likely(!len || BOUNDARY_OK(addr, = len)))
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return _s= dhci_adma_write_desc(host, desc, addr, len, cmd);
> > +
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0offset =3D addr & (SZ_128M - 1);<= br> > > +=C2=A0 =C2=A0 =C2=A0 =C2=A0tmplen =3D SZ_128M - offset;
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0_sdhci_adma_write_desc(host, desc, ad= dr, tmplen, cmd);
> > +
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0addr +=3D tmplen;
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0len -=3D tmplen;
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0desc +=3D host->desc_sz;
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0_sdhci_adma_write_desc(host, desc, ad= dr, len, cmd);
> > +
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0return host->desc_sz * 2;
> > +}
> > +
> >=C2=A0 static const struct sdhci_ops sdhci_dwcmshc_ops =3D {
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.set_clock=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D sdhci_set_clock,
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.set_bus_width=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =3D sdhci_set_bus_width,
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.set_uhs_signaling=C2=A0 =C2=A0 = =C2=A0 =3D sdhci_set_uhs_signaling,
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.get_max_clock=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =3D sdhci_pltfm_clk_get_max_clock,
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.reset=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D sdhci_reset,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0.adma_write_desc=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =3D dwcmshc_adma_write_desc,
> >=C2=A0 };
> >
> >=C2=A0 static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = =3D {
> > @@ -36,12 +67,24 @@ static int dwcmshc_probe(struct platform_devi= ce *pdev)
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0struct sdhci_host *host;
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0struct dwcmshc_priv *priv;
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int err;
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0u32 extra;
> >
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0host =3D sdhci_pltfm_init(pdev, = &sdhci_dwcmshc_pdata,
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sizeof(struct dwcmshc_p= riv));
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (IS_ERR(host))
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0retu= rn PTR_ERR(host);
> >
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0/*
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 * The DMA descriptor table number is= calculated as the maximum
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 * number of segments times 2, to all= ow for an alignment
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 * descriptor for each segment, plus = 1 for a nop end descriptor,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 * plus extra number for cross 128M b= oundary handling.
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 */
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0extra =3D DIV_ROUND_UP(totalram_pages= , SZ_128M / PAGE_SIZE);
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0if (extra > SDHCI_MAX_SEGS)
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0extra =3D= SDHCI_MAX_SEGS;
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0host->adma_table_num =3D SDHCI_MAX= _SEGS * 2 + 1 + extra;
> > +
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pltfm_host =3D sdhci_priv(host);=
> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0priv =3D sdhci_pltfm_priv(pltfm_= host);
> >
> > --
> > 2.18.0
> >
> >=C2=A0


--000000000000e2ee1c05722ed231--