Received: by 2002:ac0:a5a7:0:0:0:0:0 with SMTP id m36-v6csp3711952imm; Mon, 30 Jul 2018 01:59:32 -0700 (PDT) X-Google-Smtp-Source: AAOMgpenoST07NB8QMpCSn4uL6Vty+BFm1wUGKS2kcsdNX/A6eI07xcyKdcxx0/W8t4s3HMWBI2P X-Received: by 2002:a62:5f82:: with SMTP id t124-v6mr17089559pfb.223.1532941172185; Mon, 30 Jul 2018 01:59:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532941172; cv=none; d=google.com; s=arc-20160816; b=0dwD2vhl9ksp4Knwjxvb+t2qsrWqFtQ4maE1cwlMmxJlVFBks43V133qJIeKwfPrsp nAJrXegHM3Vj8t9+aiYmII/oKSl4j85ZIDnwwoaRNmQXRhU8wuAKeyFdh+767PpLepNy lcZ85ED/PVHK3bYkkKcOR4HUgLMUGeB12Sex6Xk7RUNK6G/FnMycYerPUarzHicR84UB 8v9GIzqIctyzpiddFwf9GoOzOL87mr8MBzvCcVwYI8fM8At0c7CH72WpLMMtFfkFPmde 0B9YFXTVivrUNaZ32gU2LbG9uGScBTgSwX9RyToCuEy4bPIWSYhdQdpfEDRmRL+GNelQ erVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:from:references:cc:to:subject:arc-authentication-results; bh=oHDhf627lDqU+EQ7YeoQ+1gKHVgBVSpwLJwimM63gQI=; b=BJkEz18wT+en9s/eTCbi0mfy0NYL6wW2yuQSCv/4McCREq+UGGmUSXnh99l+Ji7E8o AYODje2zcyytrwYHJsiC/9f/hsZr/6o4P3t3/cgMAq0AsLStHvv3A1QLuQ856qi2AP9a Cf8k0+9S90eVAANwcP1r2GCZfZKtLv8mP/tVsKnwASsdRPpdo3hQ2do1oLb9Zv/cYV72 E/xb/GRfdwbfz0jljKSs8lyX0tJIOI3Urd5bCJU9gFNjeZFgDn1qww/gXHYE9t+vgDRk 0YuKkGghkw0vgMHmSmUpYz3Mg6GxBF1eX3hbMWCTkKoH6GiZ4Lerxx5TiOhLm8aBxLLt aaYg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y187-v6si9891732pgd.459.2018.07.30.01.59.17; Mon, 30 Jul 2018 01:59:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726687AbeG3KcM (ORCPT + 99 others); Mon, 30 Jul 2018 06:32:12 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15146 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726565AbeG3KcM (ORCPT ); Mon, 30 Jul 2018 06:32:12 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Mon, 30 Jul 2018 01:58:10 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 30 Jul 2018 01:58:13 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 30 Jul 2018 01:58:13 -0700 Received: from [10.21.132.122] (172.20.13.39) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 30 Jul 2018 08:58:11 +0000 Subject: Re: [PATCH 1/4] ASoC: tegra: i2s: Fix typo/broken macro To: Jorge Sanjuan , , CC: , , , , References: <20180727125931.9794-1-jorge.sanjuan@codethink.co.uk> <20180727125931.9794-2-jorge.sanjuan@codethink.co.uk> From: Jon Hunter Message-ID: Date: Mon, 30 Jul 2018 09:58:09 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20180727125931.9794-2-jorge.sanjuan@codethink.co.uk> X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL103.nvidia.com (172.20.187.11) To HQMAIL101.nvidia.com (172.20.187.10) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 27/07/18 13:59, Jorge Sanjuan wrote: > From: Edward Cragg > > Fix typo in macro TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK. > > Signed-off-by: Edward Cragg > Signed-off-by: Jorge Sanjuan > --- > sound/soc/tegra/tegra30_i2s.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/sound/soc/tegra/tegra30_i2s.h b/sound/soc/tegra/tegra30_i2s.h > index 774fc6ad2026..2e561e946de2 100644 > --- a/sound/soc/tegra/tegra30_i2s.h > +++ b/sound/soc/tegra/tegra30_i2s.h > @@ -173,7 +173,7 @@ > /* Number of slots in frame, minus 1 */ > #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT 16 > #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US 7 > -#define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK (TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOT_MASK_US << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOT_SHIFT) > +#define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK (TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT) > > /* TDM mode slot enable bitmask */ > #define TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT 8 Thanks for fixing. Reviewed-by: Jon Hunter Cheers Jon -- nvpublic