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[209.132.180.67]) by mx.google.com with ESMTP id h2-v6si10449948plh.339.2018.07.30.08.45.53; Mon, 30 Jul 2018 08:46:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731359AbeG3RTd convert rfc822-to-8bit (ORCPT + 99 others); Mon, 30 Jul 2018 13:19:33 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:16316 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726843AbeG3RTd (ORCPT ); Mon, 30 Jul 2018 13:19:33 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Mon, 30 Jul 2018 08:43:47 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 30 Jul 2018 08:43:59 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 30 Jul 2018 08:43:59 -0700 Received: from dhcp-10-21-25-168 (10.21.25.201) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 30 Jul 2018 15:43:56 +0000 Date: Mon, 30 Jul 2018 18:43:51 +0300 From: Aapo Vienamo To: Ulf Hansson CC: Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Adrian Hunter , "Mikko Perttunen" , "linux-mmc@vger.kernel.org" , , , Linux Kernel Mailing List Subject: Re: [PATCH v2 00/10] Tegra SDHCI update the pad autocal procedure Message-ID: <20180730184351.5044cb6e@dhcp-10-21-25-168> In-Reply-To: References: <1532608016-14319-1-git-send-email-avienamo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 8BIT X-Originating-IP: [10.21.25.201] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To HQMAIL101.nvidia.com (172.20.187.10) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 30 Jul 2018 17:07:59 +0200 Ulf Hansson wrote: > On 26 July 2018 at 14:26, Aapo Vienamo wrote: > > Hi all, > > > > Update the tegra_sdhci_pad_autocalib() pad drive strength calibration > > procedure to match the ones specified in the TRMs of the more recent > > SoCs. This was tested on Tegra186, Tegra210, and Tegra124, although it > > should not break things older generations either. > > > > This series depends on the "Tegra SDHCI enable 1.8 V signaling on > > Tegar210 and Tegra186" series posted earlier. > > According to the cover letter of the above series, it states that it > depends on $subject series. A circular dependency. :-) The dependency chain goes like this: "Tegra SDHCI update the pad autocal procedure" -> "Tegra SDHCI enable 1.8 V signaling on Tegar210 and Tegra186" -> "Tegra PMC pinctrl pad configuration". > In fact, there should be no dependency at all or else there seems to > be a DT compatibility problem here... From a functionality perspective there's no strict dependency, however, I don't think "[PATCH v2 09/10] mmc: tegra: Perform pad calibration after voltage switch" can be applied cleanly without "[PATCH v2 03/10] mmc: tegra: Reconfigure pad voltages during voltage switching" from the "Tegra SDHCI enable 1.8 V signaling on Tegar210 and Tegra186" series. > Anyway, I think it actually makes sense to fold in all changes into > one series. Make sure the dt-doc changes comes first, then the driver > changes and finally arm64/dts changes. This should make it easy to > follow the review and I can pick the mmc parts and the soc maintainer > can pick the arm64/dts changes. I've sent the changes in multiple part because I've been working on further changes to the driver while the previous parts have been getting reviewed. This is still the case and there's still going to be at least one more series which adds support for HS200 tuning and some smaller changes after it. However, the HS200 work is probably going to be ready for review in a day or two. I can send these as a one series from now on, although at this point it would be 27 patches in total and even more with the HS200 patches. I can do that if you prefer to do it that way. Makes my life somewhat easier too. -Aapo