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[209.132.180.67]) by mx.google.com with ESMTP id u2-v6si10590683pge.585.2018.07.30.10.10.13; Mon, 30 Jul 2018 10:10:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730802AbeG3Snr convert rfc822-to-8bit (ORCPT + 99 others); Mon, 30 Jul 2018 14:43:47 -0400 Received: from mga05.intel.com ([192.55.52.43]:38256 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726762AbeG3Snq (ORCPT ); Mon, 30 Jul 2018 14:43:46 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Jul 2018 10:07:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,422,1526367600"; d="scan'208";a="79063553" Received: from orsmsx104.amr.corp.intel.com ([10.22.225.131]) by orsmga002.jf.intel.com with ESMTP; 30 Jul 2018 10:07:18 -0700 Received: from orsmsx160.amr.corp.intel.com (10.22.226.43) by ORSMSX104.amr.corp.intel.com (10.22.225.131) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 30 Jul 2018 10:07:17 -0700 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.242]) by ORSMSX160.amr.corp.intel.com ([169.254.13.2]) with mapi id 14.03.0319.002; Mon, 30 Jul 2018 10:07:17 -0700 From: "Prakhya, Sai Praneeth" To: Thomas Gleixner , "Hansen, Dave" CC: "x86@kernel.org" , "linux-kernel@vger.kernel.org" , "Chen, Tim C" , "Shankar, Ravi V" , Ingo Molnar Subject: RE: [PATCH] x86/speculation: Support Enhanced IBRS on future CPUs Thread-Topic: [PATCH] x86/speculation: Support Enhanced IBRS on future CPUs Thread-Index: AQHUI5CB01KrMjG5ck2pZsXG/OeZWaSoLwKAgAAikICAACmqAP//jMTw Date: Mon, 30 Jul 2018 17:07:17 +0000 Message-ID: References: <1532465636-25240-1-git-send-email-sai.praneeth.prakhya@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNDkzY2VjMDItNjJjYS00Yzk2LWIwNzItNjI3ZmZkNjQxODcyIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiVXRhVDFKSm9pZ1M2OWRyb3VVM0ZWenZXb2M0eHp3Q200MUZ0ZCtaMncxeDVqbEtNK1RwXC9VWUVjNVdJXC9rdG1EIn0= x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.22.254.140] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > >> From: Sai Praneeth Some future > > >> Intel processors may support "Enhanced IBRS" which is an "always > > >> on" mode i.e. IBRS bit in SPEC_CTRL MSR is enabled once and never > > >> disabled. According to specification[1], this should simplify > > >> software enabling and improve performance. > > > SHOULD is not really helpful. The question is whether it does > > > improve performance in practice or not. You really want to add > > > numbers comparing retpoutine and enhanced IBRS. > > > > One thing to remember from Intel's retpoline paper: > > > > > Retpoline is known to be an effective branch target injection > > > (Spectre variant 2) mitigation on Intel processors belonging to > > > family 6 (enumerated by the CPUID instruction) that do not have > > > support for enhanced IBRS. On processors that support enhanced IBRS, > > > it should be used for mitigation instead of retpoline. > > > > That's both a statement of "Intel would like you to use enhanced IBRS > > over retpoline where available" and "retpoline provides less > > mitigation on processors with enhanced IBRS compared to those without". > > > > In other words, we can _do_ performance deltas, but they won't be as > > meaningful because they won't really have apples-to-apples mitigation > > properties. > > Fair enough, but this wants to be spelled out in the change log explicitely instead > of unspecific blurbs. Sure! Makes sense. Would you like me to send a V2 with updated change log? Regards, Sai