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[209.132.180.67]) by mx.google.com with ESMTP id w2-v6si10171888plp.441.2018.07.30.10.11.56; Mon, 30 Jul 2018 10:12:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727597AbeG3SrE (ORCPT + 99 others); Mon, 30 Jul 2018 14:47:04 -0400 Received: from Galois.linutronix.de ([146.0.238.70]:57026 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726762AbeG3SrE (ORCPT ); Mon, 30 Jul 2018 14:47:04 -0400 Received: from p4fea5a5a.dip0.t-ipconnect.de ([79.234.90.90] helo=nanos) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1fkBhJ-0004BC-Jh; Mon, 30 Jul 2018 19:11:05 +0200 Date: Mon, 30 Jul 2018 19:11:05 +0200 (CEST) From: Thomas Gleixner To: "Prakhya, Sai Praneeth" cc: "Hansen, Dave" , "x86@kernel.org" , "linux-kernel@vger.kernel.org" , "Chen, Tim C" , "Shankar, Ravi V" , Ingo Molnar Subject: RE: [PATCH] x86/speculation: Support Enhanced IBRS on future CPUs In-Reply-To: Message-ID: References: <1532465636-25240-1-git-send-email-sai.praneeth.prakhya@intel.com> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 30 Jul 2018, Prakhya, Sai Praneeth wrote: > > > >> From: Sai Praneeth Some future > > > >> Intel processors may support "Enhanced IBRS" which is an "always > > > >> on" mode i.e. IBRS bit in SPEC_CTRL MSR is enabled once and never > > > >> disabled. According to specification[1], this should simplify > > > >> software enabling and improve performance. > > > > SHOULD is not really helpful. The question is whether it does > > > > improve performance in practice or not. You really want to add > > > > numbers comparing retpoutine and enhanced IBRS. > > > > > > One thing to remember from Intel's retpoline paper: > > > > > > > Retpoline is known to be an effective branch target injection > > > > (Spectre variant 2) mitigation on Intel processors belonging to > > > > family 6 (enumerated by the CPUID instruction) that do not have > > > > support for enhanced IBRS. On processors that support enhanced IBRS, > > > > it should be used for mitigation instead of retpoline. > > > > > > That's both a statement of "Intel would like you to use enhanced IBRS > > > over retpoline where available" and "retpoline provides less > > > mitigation on processors with enhanced IBRS compared to those without". > > > > > > In other words, we can _do_ performance deltas, but they won't be as > > > meaningful because they won't really have apples-to-apples mitigation > > > properties. > > > > Fair enough, but this wants to be spelled out in the change log explicitely instead > > of unspecific blurbs. > > Sure! Makes sense. Would you like me to send a V2 with updated change log? Of course.