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a=rsa-sha256; c=relaxed/relaxed; d=wavesemi.onmicrosoft.com; s=selector1-wavecomp-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zNtU6ELofLLfbu/zIMIX6iw8NDxAJLorV2/LCBEU3EI=; b=FnxsVfQzLg4lAWT9Fswmq+UrDXD/oEMVtH9Yxysej05H0XROjKs0fklDE68jUGOTyrDAkVwEwSkI7FALwdkmibOgGNs/UIzZ5X7vYlEeRZNaTXkGQzFNPkTtt0Wno7lcK0U8cRBxhqiCCpR8evDbs4y6VlJe+QbKby7wxAQHIio= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=pburton@wavecomp.com; Received: from localhost (4.16.204.77) by BN7PR08MB4931.namprd08.prod.outlook.com (2603:10b6:408:28::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.995.16; Mon, 30 Jul 2018 17:35:24 +0000 Date: Mon, 30 Jul 2018 10:35:22 -0700 From: Paul Burton To: Quentin Schulz Cc: alexandre.belloni@bootlin.com, robh+dt@kernel.org, mark.rutland@arm.com, linus.walleij@linaro.org, ralf@linux-mips.org, jhogan@kernel.org, linux-gpio@vger.kernel.org, linux-mips@linux-mips.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, thomas.petazzoni@bootlin.com Subject: Re: [PATCH 1/2] MIPS: mscc: ocelot: add interrupt controller properties to GPIO controller Message-ID: <20180730173521.fr6be2kw7irk5jbp@pburton-laptop> References: <20180725122621.31713-1-quentin.schulz@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; 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Paul